1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "aldebaran.h"
25 #include "amdgpu_reset.h"
26 #include "amdgpu_amdkfd.h"
27 #include "amdgpu_dpm.h"
28 #include "amdgpu_job.h"
29 #include "amdgpu_ring.h"
30 #include "amdgpu_ras.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_xgmi.h"
33
aldebaran_is_mode2_default(struct amdgpu_reset_control * reset_ctl)34 static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
35 {
36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
37
38 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) &&
39 adev->gmc.xgmi.connected_to_cpu))
40 return true;
41
42 return false;
43 }
44
45 static struct amdgpu_reset_handler *
aldebaran_get_reset_handler(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)46 aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
47 struct amdgpu_reset_context *reset_context)
48 {
49 struct amdgpu_reset_handler *handler;
50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
51 int i;
52
53 if (reset_context->method == AMD_RESET_METHOD_NONE) {
54 if (aldebaran_is_mode2_default(reset_ctl))
55 reset_context->method = AMD_RESET_METHOD_MODE2;
56 else
57 reset_context->method = amdgpu_asic_reset_method(adev);
58 }
59
60 if (reset_context->method != AMD_RESET_METHOD_NONE) {
61 dev_dbg(adev->dev, "Getting reset handler for method %d\n",
62 reset_context->method);
63 for_each_handler(i, handler, reset_ctl) {
64 if (handler->reset_method == reset_context->method)
65 return handler;
66 }
67 }
68
69 dev_dbg(adev->dev, "Reset handler not found!\n");
70
71 return NULL;
72 }
73
aldebaran_mode2_suspend_ip(struct amdgpu_device * adev)74 static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev)
75 {
76 int r, i;
77
78 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
79 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
80
81 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
82 if (!(adev->ip_blocks[i].version->type ==
83 AMD_IP_BLOCK_TYPE_GFX ||
84 adev->ip_blocks[i].version->type ==
85 AMD_IP_BLOCK_TYPE_SDMA))
86 continue;
87
88 r = adev->ip_blocks[i].version->funcs->suspend(adev);
89
90 if (r) {
91 dev_err(adev->dev,
92 "suspend of IP block <%s> failed %d\n",
93 adev->ip_blocks[i].version->funcs->name, r);
94 return r;
95 }
96
97 adev->ip_blocks[i].status.hw = false;
98 }
99
100 return 0;
101 }
102
103 static int
aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)104 aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
105 struct amdgpu_reset_context *reset_context)
106 {
107 int r = 0;
108 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
109
110 dev_dbg(adev->dev, "Aldebaran prepare hw context\n");
111 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
112 if (!amdgpu_sriov_vf(adev))
113 r = aldebaran_mode2_suspend_ip(adev);
114
115 return r;
116 }
117
aldebaran_async_reset(struct work_struct * work)118 static void aldebaran_async_reset(struct work_struct *work)
119 {
120 struct amdgpu_reset_handler *handler;
121 struct amdgpu_reset_control *reset_ctl =
122 container_of(work, struct amdgpu_reset_control, reset_work);
123 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
124 int i;
125
126 for_each_handler(i, handler, reset_ctl) {
127 if (handler->reset_method == reset_ctl->active_reset) {
128 dev_dbg(adev->dev, "Resetting device\n");
129 handler->do_reset(adev);
130 break;
131 }
132 }
133 }
134
aldebaran_mode2_reset(struct amdgpu_device * adev)135 static int aldebaran_mode2_reset(struct amdgpu_device *adev)
136 {
137 /* disable BM */
138 pci_clear_master(adev->pdev);
139 adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev);
140 return adev->asic_reset_res;
141 }
142
143 static int
aldebaran_mode2_perform_reset(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)144 aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
145 struct amdgpu_reset_context *reset_context)
146 {
147 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
148 struct list_head *reset_device_list = reset_context->reset_device_list;
149 struct amdgpu_device *tmp_adev = NULL;
150 int r = 0;
151
152 dev_dbg(adev->dev, "aldebaran perform hw reset\n");
153
154 if (reset_device_list == NULL)
155 return -EINVAL;
156
157 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) &&
158 reset_context->hive == NULL) {
159 /* Wrong context, return error */
160 return -EINVAL;
161 }
162
163 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
164 mutex_lock(&tmp_adev->reset_cntl->reset_lock);
165 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;
166 }
167 /*
168 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch
169 * them together so that they can be completed asynchronously on multiple nodes
170 */
171 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
172 /* For XGMI run all resets in parallel to speed up the process */
173 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
174 if (!queue_work(system_unbound_wq,
175 &tmp_adev->reset_cntl->reset_work))
176 r = -EALREADY;
177 } else
178 r = aldebaran_mode2_reset(tmp_adev);
179 if (r) {
180 dev_err(tmp_adev->dev,
181 "ASIC reset failed with error, %d for drm dev, %s",
182 r, adev_to_drm(tmp_adev)->unique);
183 break;
184 }
185 }
186
187 /* For XGMI wait for all resets to complete before proceed */
188 if (!r) {
189 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
190 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
191 flush_work(&tmp_adev->reset_cntl->reset_work);
192 r = tmp_adev->asic_reset_res;
193 if (r)
194 break;
195 }
196 }
197 }
198
199 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
200 mutex_unlock(&tmp_adev->reset_cntl->reset_lock);
201 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;
202 }
203
204 return r;
205 }
206
aldebaran_mode2_restore_ip(struct amdgpu_device * adev)207 static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)
208 {
209 struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM];
210 struct amdgpu_firmware_info *ucode;
211 struct amdgpu_ip_block *cmn_block;
212 int ucode_count = 0;
213 int i, r;
214
215 dev_dbg(adev->dev, "Reloading ucodes after reset\n");
216 for (i = 0; i < adev->firmware.max_ucodes; i++) {
217 ucode = &adev->firmware.ucode[i];
218 if (!ucode->fw)
219 continue;
220 switch (ucode->ucode_id) {
221 case AMDGPU_UCODE_ID_SDMA0:
222 case AMDGPU_UCODE_ID_SDMA1:
223 case AMDGPU_UCODE_ID_SDMA2:
224 case AMDGPU_UCODE_ID_SDMA3:
225 case AMDGPU_UCODE_ID_SDMA4:
226 case AMDGPU_UCODE_ID_SDMA5:
227 case AMDGPU_UCODE_ID_SDMA6:
228 case AMDGPU_UCODE_ID_SDMA7:
229 case AMDGPU_UCODE_ID_CP_MEC1:
230 case AMDGPU_UCODE_ID_CP_MEC1_JT:
231 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
232 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
233 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
234 case AMDGPU_UCODE_ID_RLC_G:
235 ucode_list[ucode_count++] = ucode;
236 break;
237 default:
238 break;
239 }
240 }
241
242 /* Reinit NBIF block */
243 cmn_block =
244 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON);
245 if (unlikely(!cmn_block)) {
246 dev_err(adev->dev, "Failed to get BIF handle\n");
247 return -EINVAL;
248 }
249 r = cmn_block->version->funcs->resume(adev);
250 if (r)
251 return r;
252
253 /* Reinit GFXHUB */
254 adev->gfxhub.funcs->init(adev);
255 r = adev->gfxhub.funcs->gart_enable(adev);
256 if (r) {
257 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
258 return r;
259 }
260
261 /* Reload GFX firmware */
262 r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count);
263 if (r) {
264 dev_err(adev->dev, "GFX ucode load failed after reset\n");
265 return r;
266 }
267
268 /* Resume RLC, FW needs RLC alive to complete reset process */
269 adev->gfx.rlc.funcs->resume(adev);
270
271 /* Wait for FW reset event complete */
272 r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);
273 if (r) {
274 dev_err(adev->dev,
275 "Failed to get response from firmware after reset\n");
276 return r;
277 }
278
279 for (i = 0; i < adev->num_ip_blocks; i++) {
280 if (!(adev->ip_blocks[i].version->type ==
281 AMD_IP_BLOCK_TYPE_GFX ||
282 adev->ip_blocks[i].version->type ==
283 AMD_IP_BLOCK_TYPE_SDMA))
284 continue;
285 r = adev->ip_blocks[i].version->funcs->resume(adev);
286 if (r) {
287 dev_err(adev->dev,
288 "resume of IP block <%s> failed %d\n",
289 adev->ip_blocks[i].version->funcs->name, r);
290 return r;
291 }
292
293 adev->ip_blocks[i].status.hw = true;
294 }
295
296 for (i = 0; i < adev->num_ip_blocks; i++) {
297 if (!(adev->ip_blocks[i].version->type ==
298 AMD_IP_BLOCK_TYPE_GFX ||
299 adev->ip_blocks[i].version->type ==
300 AMD_IP_BLOCK_TYPE_SDMA ||
301 adev->ip_blocks[i].version->type ==
302 AMD_IP_BLOCK_TYPE_COMMON))
303 continue;
304
305 if (adev->ip_blocks[i].version->funcs->late_init) {
306 r = adev->ip_blocks[i].version->funcs->late_init(
307 (void *)adev);
308 if (r) {
309 dev_err(adev->dev,
310 "late_init of IP block <%s> failed %d after reset\n",
311 adev->ip_blocks[i].version->funcs->name,
312 r);
313 return r;
314 }
315 }
316 adev->ip_blocks[i].status.late_initialized = true;
317 }
318
319 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
320 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
321
322 return r;
323 }
324
325 static int
aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control * reset_ctl,struct amdgpu_reset_context * reset_context)326 aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
327 struct amdgpu_reset_context *reset_context)
328 {
329 struct list_head *reset_device_list = reset_context->reset_device_list;
330 struct amdgpu_device *tmp_adev = NULL;
331 struct amdgpu_ras *con;
332 int r;
333
334 if (reset_device_list == NULL)
335 return -EINVAL;
336
337 if (amdgpu_ip_version(reset_context->reset_req_dev, MP1_HWIP, 0) ==
338 IP_VERSION(13, 0, 2) &&
339 reset_context->hive == NULL) {
340 /* Wrong context, return error */
341 return -EINVAL;
342 }
343
344 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
345 dev_info(tmp_adev->dev,
346 "GPU reset succeeded, trying to resume\n");
347 r = aldebaran_mode2_restore_ip(tmp_adev);
348 if (r)
349 goto end;
350
351 /*
352 * Add this ASIC as tracked as reset was already
353 * complete successfully.
354 */
355 amdgpu_register_gpu_instance(tmp_adev);
356
357 /* Resume RAS, ecc_irq */
358 con = amdgpu_ras_get_context(tmp_adev);
359 if (!amdgpu_sriov_vf(tmp_adev) && con) {
360 if (tmp_adev->sdma.ras &&
361 tmp_adev->sdma.ras->ras_block.ras_late_init) {
362 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,
363 &tmp_adev->sdma.ras->ras_block.ras_comm);
364 if (r) {
365 dev_err(tmp_adev->dev, "SDMA failed to execute ras_late_init! ret:%d\n", r);
366 goto end;
367 }
368 }
369
370 if (tmp_adev->gfx.ras &&
371 tmp_adev->gfx.ras->ras_block.ras_late_init) {
372 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
373 &tmp_adev->gfx.ras->ras_block.ras_comm);
374 if (r) {
375 dev_err(tmp_adev->dev, "GFX failed to execute ras_late_init! ret:%d\n", r);
376 goto end;
377 }
378 }
379 }
380
381 amdgpu_ras_resume(tmp_adev);
382
383 /* Update PSP FW topology after reset */
384 if (reset_context->hive &&
385 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
386 r = amdgpu_xgmi_update_topology(reset_context->hive,
387 tmp_adev);
388
389 if (!r) {
390 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
391
392 r = amdgpu_ib_ring_tests(tmp_adev);
393 if (r) {
394 dev_err(tmp_adev->dev,
395 "ib ring test failed (%d).\n", r);
396 r = -EAGAIN;
397 tmp_adev->asic_reset_res = r;
398 goto end;
399 }
400 }
401 }
402
403 end:
404 return r;
405 }
406
407 static struct amdgpu_reset_handler aldebaran_mode2_handler = {
408 .reset_method = AMD_RESET_METHOD_MODE2,
409 .prepare_env = NULL,
410 .prepare_hwcontext = aldebaran_mode2_prepare_hwcontext,
411 .perform_reset = aldebaran_mode2_perform_reset,
412 .restore_hwcontext = aldebaran_mode2_restore_hwcontext,
413 .restore_env = NULL,
414 .do_reset = aldebaran_mode2_reset,
415 };
416
417 static struct amdgpu_reset_handler
418 *aldebaran_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = {
419 &aldebaran_mode2_handler,
420 };
421
aldebaran_reset_init(struct amdgpu_device * adev)422 int aldebaran_reset_init(struct amdgpu_device *adev)
423 {
424 struct amdgpu_reset_control *reset_ctl;
425
426 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
427 if (!reset_ctl)
428 return -ENOMEM;
429
430 reset_ctl->handle = adev;
431 reset_ctl->async_reset = aldebaran_async_reset;
432 reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
433 reset_ctl->get_reset_handler = aldebaran_get_reset_handler;
434
435 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
436 /* Only mode2 is handled through reset control now */
437 reset_ctl->reset_handlers = &aldebaran_rst_handlers;
438
439 adev->reset_cntl = reset_ctl;
440
441 return 0;
442 }
443
aldebaran_reset_fini(struct amdgpu_device * adev)444 int aldebaran_reset_fini(struct amdgpu_device *adev)
445 {
446 kfree(adev->reset_cntl);
447 adev->reset_cntl = NULL;
448 return 0;
449 }
450