1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/bitops.h> 3 #include <linux/types.h> 4 #include <linux/slab.h> 5 #include <linux/sched/clock.h> 6 7 #include <asm/cpu_entry_area.h> 8 #include <asm/debugreg.h> 9 #include <asm/perf_event.h> 10 #include <asm/tlbflush.h> 11 #include <asm/insn.h> 12 #include <asm/io.h> 13 #include <asm/timer.h> 14 15 #include "../perf_event.h" 16 17 /* Waste a full page so it can be mapped into the cpu_entry_area */ 18 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); 19 20 /* The size of a BTS record in bytes: */ 21 #define BTS_RECORD_SIZE 24 22 23 #define PEBS_FIXUP_SIZE PAGE_SIZE 24 25 /* 26 * pebs_record_32 for p4 and core not supported 27 28 struct pebs_record_32 { 29 u32 flags, ip; 30 u32 ax, bc, cx, dx; 31 u32 si, di, bp, sp; 32 }; 33 34 */ 35 36 union intel_x86_pebs_dse { 37 u64 val; 38 struct { 39 unsigned int ld_dse:4; 40 unsigned int ld_stlb_miss:1; 41 unsigned int ld_locked:1; 42 unsigned int ld_data_blk:1; 43 unsigned int ld_addr_blk:1; 44 unsigned int ld_reserved:24; 45 }; 46 struct { 47 unsigned int st_l1d_hit:1; 48 unsigned int st_reserved1:3; 49 unsigned int st_stlb_miss:1; 50 unsigned int st_locked:1; 51 unsigned int st_reserved2:26; 52 }; 53 struct { 54 unsigned int st_lat_dse:4; 55 unsigned int st_lat_stlb_miss:1; 56 unsigned int st_lat_locked:1; 57 unsigned int ld_reserved3:26; 58 }; 59 struct { 60 unsigned int mtl_dse:5; 61 unsigned int mtl_locked:1; 62 unsigned int mtl_stlb_miss:1; 63 unsigned int mtl_fwd_blk:1; 64 unsigned int ld_reserved4:24; 65 }; 66 struct { 67 unsigned int lnc_dse:8; 68 unsigned int ld_reserved5:2; 69 unsigned int lnc_stlb_miss:1; 70 unsigned int lnc_locked:1; 71 unsigned int lnc_data_blk:1; 72 unsigned int lnc_addr_blk:1; 73 unsigned int ld_reserved6:18; 74 }; 75 }; 76 77 78 /* 79 * Map PEBS Load Latency Data Source encodings to generic 80 * memory data source information 81 */ 82 #define P(a, b) PERF_MEM_S(a, b) 83 #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) 84 #define LEVEL(x) P(LVLNUM, x) 85 #define REM P(REMOTE, REMOTE) 86 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) 87 88 /* Version for Sandy Bridge and later */ 89 static u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX] = { 90 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ 91 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */ 92 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ 93 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ 94 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ 95 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ 96 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ 97 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ 98 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ 99 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ 100 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ 101 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ 102 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */ 103 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */ 104 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */ 105 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */ 106 }; 107 108 /* Patch up minor differences in the bits */ intel_pmu_pebs_data_source_nhm(void)109 void __init intel_pmu_pebs_data_source_nhm(void) 110 { 111 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); 112 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 113 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 114 } 115 __intel_pmu_pebs_data_source_skl(bool pmem,u64 * data_source)116 static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_source) 117 { 118 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4); 119 120 data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT); 121 data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); 122 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); 123 data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); 124 data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); 125 } 126 intel_pmu_pebs_data_source_skl(bool pmem)127 void __init intel_pmu_pebs_data_source_skl(bool pmem) 128 { 129 __intel_pmu_pebs_data_source_skl(pmem, pebs_data_source); 130 } 131 __intel_pmu_pebs_data_source_grt(u64 * data_source)132 static void __init __intel_pmu_pebs_data_source_grt(u64 *data_source) 133 { 134 data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); 135 data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 136 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); 137 } 138 intel_pmu_pebs_data_source_grt(void)139 void __init intel_pmu_pebs_data_source_grt(void) 140 { 141 __intel_pmu_pebs_data_source_grt(pebs_data_source); 142 } 143 intel_pmu_pebs_data_source_adl(void)144 void __init intel_pmu_pebs_data_source_adl(void) 145 { 146 u64 *data_source; 147 148 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; 149 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 150 __intel_pmu_pebs_data_source_skl(false, data_source); 151 152 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; 153 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 154 __intel_pmu_pebs_data_source_grt(data_source); 155 } 156 __intel_pmu_pebs_data_source_cmt(u64 * data_source)157 static void __init __intel_pmu_pebs_data_source_cmt(u64 *data_source) 158 { 159 data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); 160 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 161 data_source[0x0a] = OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE); 162 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); 163 data_source[0x0c] = OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD); 164 data_source[0x0d] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM); 165 } 166 intel_pmu_pebs_data_source_mtl(void)167 void __init intel_pmu_pebs_data_source_mtl(void) 168 { 169 u64 *data_source; 170 171 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; 172 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 173 __intel_pmu_pebs_data_source_skl(false, data_source); 174 175 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; 176 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 177 __intel_pmu_pebs_data_source_cmt(data_source); 178 } 179 intel_pmu_pebs_data_source_cmt(void)180 void __init intel_pmu_pebs_data_source_cmt(void) 181 { 182 __intel_pmu_pebs_data_source_cmt(pebs_data_source); 183 } 184 185 /* Version for Lion Cove and later */ 186 static u64 lnc_pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX] = { 187 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* 0x00: ukn L3 */ 188 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 hit */ 189 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x02: L1 hit */ 190 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x03: LFB/L1 Miss Handling Buffer hit */ 191 0, /* 0x04: Reserved */ 192 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x05: L2 Hit */ 193 OP_LH | LEVEL(L2_MHB) | P(SNOOP, NONE), /* 0x06: L2 Miss Handling Buffer Hit */ 194 0, /* 0x07: Reserved */ 195 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x08: L3 Hit */ 196 0, /* 0x09: Reserved */ 197 0, /* 0x0a: Reserved */ 198 0, /* 0x0b: Reserved */ 199 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD), /* 0x0c: L3 Hit Snoop Fwd */ 200 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0d: L3 Hit Snoop HitM */ 201 0, /* 0x0e: Reserved */ 202 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0f: L3 Miss Snoop HitM */ 203 OP_LH | LEVEL(MSC) | P(SNOOP, NONE), /* 0x10: Memory-side Cache Hit */ 204 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE), /* 0x11: Local Memory Hit */ 205 }; 206 intel_pmu_pebs_data_source_lnl(void)207 void __init intel_pmu_pebs_data_source_lnl(void) 208 { 209 u64 *data_source; 210 211 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; 212 memcpy(data_source, lnc_pebs_data_source, sizeof(lnc_pebs_data_source)); 213 214 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; 215 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); 216 __intel_pmu_pebs_data_source_cmt(data_source); 217 } 218 precise_store_data(u64 status)219 static u64 precise_store_data(u64 status) 220 { 221 union intel_x86_pebs_dse dse; 222 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); 223 224 dse.val = status; 225 226 /* 227 * bit 4: TLB access 228 * 1 = stored missed 2nd level TLB 229 * 230 * so it either hit the walker or the OS 231 * otherwise hit 2nd level TLB 232 */ 233 if (dse.st_stlb_miss) 234 val |= P(TLB, MISS); 235 else 236 val |= P(TLB, HIT); 237 238 /* 239 * bit 0: hit L1 data cache 240 * if not set, then all we know is that 241 * it missed L1D 242 */ 243 if (dse.st_l1d_hit) 244 val |= P(LVL, HIT); 245 else 246 val |= P(LVL, MISS); 247 248 /* 249 * bit 5: Locked prefix 250 */ 251 if (dse.st_locked) 252 val |= P(LOCK, LOCKED); 253 254 return val; 255 } 256 precise_datala_hsw(struct perf_event * event,u64 status)257 static u64 precise_datala_hsw(struct perf_event *event, u64 status) 258 { 259 union perf_mem_data_src dse; 260 261 dse.val = PERF_MEM_NA; 262 263 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) 264 dse.mem_op = PERF_MEM_OP_STORE; 265 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) 266 dse.mem_op = PERF_MEM_OP_LOAD; 267 268 /* 269 * L1 info only valid for following events: 270 * 271 * MEM_UOPS_RETIRED.STLB_MISS_STORES 272 * MEM_UOPS_RETIRED.LOCK_STORES 273 * MEM_UOPS_RETIRED.SPLIT_STORES 274 * MEM_UOPS_RETIRED.ALL_STORES 275 */ 276 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { 277 if (status & 1) 278 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; 279 else 280 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS; 281 } 282 return dse.val; 283 } 284 pebs_set_tlb_lock(u64 * val,bool tlb,bool lock)285 static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock) 286 { 287 /* 288 * TLB access 289 * 0 = did not miss 2nd level TLB 290 * 1 = missed 2nd level TLB 291 */ 292 if (tlb) 293 *val |= P(TLB, MISS) | P(TLB, L2); 294 else 295 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); 296 297 /* locked prefix */ 298 if (lock) 299 *val |= P(LOCK, LOCKED); 300 } 301 302 /* Retrieve the latency data for e-core of ADL */ __grt_latency_data(struct perf_event * event,u64 status,u8 dse,bool tlb,bool lock,bool blk)303 static u64 __grt_latency_data(struct perf_event *event, u64 status, 304 u8 dse, bool tlb, bool lock, bool blk) 305 { 306 u64 val; 307 308 WARN_ON_ONCE(hybrid_pmu(event->pmu)->pmu_type == hybrid_big); 309 310 dse &= PERF_PEBS_DATA_SOURCE_GRT_MASK; 311 val = hybrid_var(event->pmu, pebs_data_source)[dse]; 312 313 pebs_set_tlb_lock(&val, tlb, lock); 314 315 if (blk) 316 val |= P(BLK, DATA); 317 else 318 val |= P(BLK, NA); 319 320 return val; 321 } 322 grt_latency_data(struct perf_event * event,u64 status)323 u64 grt_latency_data(struct perf_event *event, u64 status) 324 { 325 union intel_x86_pebs_dse dse; 326 327 dse.val = status; 328 329 return __grt_latency_data(event, status, dse.ld_dse, 330 dse.ld_locked, dse.ld_stlb_miss, 331 dse.ld_data_blk); 332 } 333 334 /* Retrieve the latency data for e-core of MTL */ cmt_latency_data(struct perf_event * event,u64 status)335 u64 cmt_latency_data(struct perf_event *event, u64 status) 336 { 337 union intel_x86_pebs_dse dse; 338 339 dse.val = status; 340 341 return __grt_latency_data(event, status, dse.mtl_dse, 342 dse.mtl_stlb_miss, dse.mtl_locked, 343 dse.mtl_fwd_blk); 344 } 345 lnc_latency_data(struct perf_event * event,u64 status)346 static u64 lnc_latency_data(struct perf_event *event, u64 status) 347 { 348 union intel_x86_pebs_dse dse; 349 union perf_mem_data_src src; 350 u64 val; 351 352 dse.val = status; 353 354 /* LNC core latency data */ 355 val = hybrid_var(event->pmu, pebs_data_source)[status & PERF_PEBS_DATA_SOURCE_MASK]; 356 if (!val) 357 val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA); 358 359 if (dse.lnc_stlb_miss) 360 val |= P(TLB, MISS) | P(TLB, L2); 361 else 362 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); 363 364 if (dse.lnc_locked) 365 val |= P(LOCK, LOCKED); 366 367 if (dse.lnc_data_blk) 368 val |= P(BLK, DATA); 369 if (dse.lnc_addr_blk) 370 val |= P(BLK, ADDR); 371 if (!dse.lnc_data_blk && !dse.lnc_addr_blk) 372 val |= P(BLK, NA); 373 374 src.val = val; 375 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) 376 src.mem_op = P(OP, STORE); 377 378 return src.val; 379 } 380 lnl_latency_data(struct perf_event * event,u64 status)381 u64 lnl_latency_data(struct perf_event *event, u64 status) 382 { 383 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 384 385 if (pmu->pmu_type == hybrid_small) 386 return cmt_latency_data(event, status); 387 388 return lnc_latency_data(event, status); 389 } 390 load_latency_data(struct perf_event * event,u64 status)391 static u64 load_latency_data(struct perf_event *event, u64 status) 392 { 393 union intel_x86_pebs_dse dse; 394 u64 val; 395 396 dse.val = status; 397 398 /* 399 * use the mapping table for bit 0-3 400 */ 401 val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse]; 402 403 /* 404 * Nehalem models do not support TLB, Lock infos 405 */ 406 if (x86_pmu.pebs_no_tlb) { 407 val |= P(TLB, NA) | P(LOCK, NA); 408 return val; 409 } 410 411 pebs_set_tlb_lock(&val, dse.ld_stlb_miss, dse.ld_locked); 412 413 /* 414 * Ice Lake and earlier models do not support block infos. 415 */ 416 if (!x86_pmu.pebs_block) { 417 val |= P(BLK, NA); 418 return val; 419 } 420 /* 421 * bit 6: load was blocked since its data could not be forwarded 422 * from a preceding store 423 */ 424 if (dse.ld_data_blk) 425 val |= P(BLK, DATA); 426 427 /* 428 * bit 7: load was blocked due to potential address conflict with 429 * a preceding store 430 */ 431 if (dse.ld_addr_blk) 432 val |= P(BLK, ADDR); 433 434 if (!dse.ld_data_blk && !dse.ld_addr_blk) 435 val |= P(BLK, NA); 436 437 return val; 438 } 439 store_latency_data(struct perf_event * event,u64 status)440 static u64 store_latency_data(struct perf_event *event, u64 status) 441 { 442 union intel_x86_pebs_dse dse; 443 union perf_mem_data_src src; 444 u64 val; 445 446 dse.val = status; 447 448 /* 449 * use the mapping table for bit 0-3 450 */ 451 val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse]; 452 453 pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked); 454 455 val |= P(BLK, NA); 456 457 /* 458 * the pebs_data_source table is only for loads 459 * so override the mem_op to say STORE instead 460 */ 461 src.val = val; 462 src.mem_op = P(OP,STORE); 463 464 return src.val; 465 } 466 467 struct pebs_record_core { 468 u64 flags, ip; 469 u64 ax, bx, cx, dx; 470 u64 si, di, bp, sp; 471 u64 r8, r9, r10, r11; 472 u64 r12, r13, r14, r15; 473 }; 474 475 struct pebs_record_nhm { 476 u64 flags, ip; 477 u64 ax, bx, cx, dx; 478 u64 si, di, bp, sp; 479 u64 r8, r9, r10, r11; 480 u64 r12, r13, r14, r15; 481 u64 status, dla, dse, lat; 482 }; 483 484 /* 485 * Same as pebs_record_nhm, with two additional fields. 486 */ 487 struct pebs_record_hsw { 488 u64 flags, ip; 489 u64 ax, bx, cx, dx; 490 u64 si, di, bp, sp; 491 u64 r8, r9, r10, r11; 492 u64 r12, r13, r14, r15; 493 u64 status, dla, dse, lat; 494 u64 real_ip, tsx_tuning; 495 }; 496 497 union hsw_tsx_tuning { 498 struct { 499 u32 cycles_last_block : 32, 500 hle_abort : 1, 501 rtm_abort : 1, 502 instruction_abort : 1, 503 non_instruction_abort : 1, 504 retry : 1, 505 data_conflict : 1, 506 capacity_writes : 1, 507 capacity_reads : 1; 508 }; 509 u64 value; 510 }; 511 512 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL 513 514 /* Same as HSW, plus TSC */ 515 516 struct pebs_record_skl { 517 u64 flags, ip; 518 u64 ax, bx, cx, dx; 519 u64 si, di, bp, sp; 520 u64 r8, r9, r10, r11; 521 u64 r12, r13, r14, r15; 522 u64 status, dla, dse, lat; 523 u64 real_ip, tsx_tuning; 524 u64 tsc; 525 }; 526 init_debug_store_on_cpu(int cpu)527 void init_debug_store_on_cpu(int cpu) 528 { 529 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 530 531 if (!ds) 532 return; 533 534 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 535 (u32)((u64)(unsigned long)ds), 536 (u32)((u64)(unsigned long)ds >> 32)); 537 } 538 fini_debug_store_on_cpu(int cpu)539 void fini_debug_store_on_cpu(int cpu) 540 { 541 if (!per_cpu(cpu_hw_events, cpu).ds) 542 return; 543 544 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); 545 } 546 547 static DEFINE_PER_CPU(void *, insn_buffer); 548 ds_update_cea(void * cea,void * addr,size_t size,pgprot_t prot)549 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot) 550 { 551 unsigned long start = (unsigned long)cea; 552 phys_addr_t pa; 553 size_t msz = 0; 554 555 pa = virt_to_phys(addr); 556 557 preempt_disable(); 558 for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE) 559 cea_set_pte(cea, pa, prot); 560 561 /* 562 * This is a cross-CPU update of the cpu_entry_area, we must shoot down 563 * all TLB entries for it. 564 */ 565 flush_tlb_kernel_range(start, start + size); 566 preempt_enable(); 567 } 568 ds_clear_cea(void * cea,size_t size)569 static void ds_clear_cea(void *cea, size_t size) 570 { 571 unsigned long start = (unsigned long)cea; 572 size_t msz = 0; 573 574 preempt_disable(); 575 for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE) 576 cea_set_pte(cea, 0, PAGE_NONE); 577 578 flush_tlb_kernel_range(start, start + size); 579 preempt_enable(); 580 } 581 dsalloc_pages(size_t size,gfp_t flags,int cpu)582 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu) 583 { 584 unsigned int order = get_order(size); 585 int node = cpu_to_node(cpu); 586 struct page *page; 587 588 page = __alloc_pages_node(node, flags | __GFP_ZERO, order); 589 return page ? page_address(page) : NULL; 590 } 591 dsfree_pages(const void * buffer,size_t size)592 static void dsfree_pages(const void *buffer, size_t size) 593 { 594 if (buffer) 595 free_pages((unsigned long)buffer, get_order(size)); 596 } 597 alloc_pebs_buffer(int cpu)598 static int alloc_pebs_buffer(int cpu) 599 { 600 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 601 struct debug_store *ds = hwev->ds; 602 size_t bsiz = x86_pmu.pebs_buffer_size; 603 int max, node = cpu_to_node(cpu); 604 void *buffer, *insn_buff, *cea; 605 606 if (!x86_pmu.pebs) 607 return 0; 608 609 buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu); 610 if (unlikely(!buffer)) 611 return -ENOMEM; 612 613 /* 614 * HSW+ already provides us the eventing ip; no need to allocate this 615 * buffer then. 616 */ 617 if (x86_pmu.intel_cap.pebs_format < 2) { 618 insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node); 619 if (!insn_buff) { 620 dsfree_pages(buffer, bsiz); 621 return -ENOMEM; 622 } 623 per_cpu(insn_buffer, cpu) = insn_buff; 624 } 625 hwev->ds_pebs_vaddr = buffer; 626 /* Update the cpu entry area mapping */ 627 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; 628 ds->pebs_buffer_base = (unsigned long) cea; 629 ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL); 630 ds->pebs_index = ds->pebs_buffer_base; 631 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); 632 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max; 633 return 0; 634 } 635 release_pebs_buffer(int cpu)636 static void release_pebs_buffer(int cpu) 637 { 638 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 639 void *cea; 640 641 if (!x86_pmu.pebs) 642 return; 643 644 kfree(per_cpu(insn_buffer, cpu)); 645 per_cpu(insn_buffer, cpu) = NULL; 646 647 /* Clear the fixmap */ 648 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; 649 ds_clear_cea(cea, x86_pmu.pebs_buffer_size); 650 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); 651 hwev->ds_pebs_vaddr = NULL; 652 } 653 alloc_bts_buffer(int cpu)654 static int alloc_bts_buffer(int cpu) 655 { 656 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 657 struct debug_store *ds = hwev->ds; 658 void *buffer, *cea; 659 int max; 660 661 if (!x86_pmu.bts) 662 return 0; 663 664 buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu); 665 if (unlikely(!buffer)) { 666 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__); 667 return -ENOMEM; 668 } 669 hwev->ds_bts_vaddr = buffer; 670 /* Update the fixmap */ 671 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; 672 ds->bts_buffer_base = (unsigned long) cea; 673 ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL); 674 ds->bts_index = ds->bts_buffer_base; 675 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE; 676 ds->bts_absolute_maximum = ds->bts_buffer_base + 677 max * BTS_RECORD_SIZE; 678 ds->bts_interrupt_threshold = ds->bts_absolute_maximum - 679 (max / 16) * BTS_RECORD_SIZE; 680 return 0; 681 } 682 release_bts_buffer(int cpu)683 static void release_bts_buffer(int cpu) 684 { 685 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu); 686 void *cea; 687 688 if (!x86_pmu.bts) 689 return; 690 691 /* Clear the fixmap */ 692 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; 693 ds_clear_cea(cea, BTS_BUFFER_SIZE); 694 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE); 695 hwev->ds_bts_vaddr = NULL; 696 } 697 alloc_ds_buffer(int cpu)698 static int alloc_ds_buffer(int cpu) 699 { 700 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store; 701 702 memset(ds, 0, sizeof(*ds)); 703 per_cpu(cpu_hw_events, cpu).ds = ds; 704 return 0; 705 } 706 release_ds_buffer(int cpu)707 static void release_ds_buffer(int cpu) 708 { 709 per_cpu(cpu_hw_events, cpu).ds = NULL; 710 } 711 release_ds_buffers(void)712 void release_ds_buffers(void) 713 { 714 int cpu; 715 716 if (!x86_pmu.bts && !x86_pmu.pebs) 717 return; 718 719 for_each_possible_cpu(cpu) 720 release_ds_buffer(cpu); 721 722 for_each_possible_cpu(cpu) { 723 /* 724 * Again, ignore errors from offline CPUs, they will no longer 725 * observe cpu_hw_events.ds and not program the DS_AREA when 726 * they come up. 727 */ 728 fini_debug_store_on_cpu(cpu); 729 } 730 731 for_each_possible_cpu(cpu) { 732 release_pebs_buffer(cpu); 733 release_bts_buffer(cpu); 734 } 735 } 736 reserve_ds_buffers(void)737 void reserve_ds_buffers(void) 738 { 739 int bts_err = 0, pebs_err = 0; 740 int cpu; 741 742 x86_pmu.bts_active = 0; 743 x86_pmu.pebs_active = 0; 744 745 if (!x86_pmu.bts && !x86_pmu.pebs) 746 return; 747 748 if (!x86_pmu.bts) 749 bts_err = 1; 750 751 if (!x86_pmu.pebs) 752 pebs_err = 1; 753 754 for_each_possible_cpu(cpu) { 755 if (alloc_ds_buffer(cpu)) { 756 bts_err = 1; 757 pebs_err = 1; 758 } 759 760 if (!bts_err && alloc_bts_buffer(cpu)) 761 bts_err = 1; 762 763 if (!pebs_err && alloc_pebs_buffer(cpu)) 764 pebs_err = 1; 765 766 if (bts_err && pebs_err) 767 break; 768 } 769 770 if (bts_err) { 771 for_each_possible_cpu(cpu) 772 release_bts_buffer(cpu); 773 } 774 775 if (pebs_err) { 776 for_each_possible_cpu(cpu) 777 release_pebs_buffer(cpu); 778 } 779 780 if (bts_err && pebs_err) { 781 for_each_possible_cpu(cpu) 782 release_ds_buffer(cpu); 783 } else { 784 if (x86_pmu.bts && !bts_err) 785 x86_pmu.bts_active = 1; 786 787 if (x86_pmu.pebs && !pebs_err) 788 x86_pmu.pebs_active = 1; 789 790 for_each_possible_cpu(cpu) { 791 /* 792 * Ignores wrmsr_on_cpu() errors for offline CPUs they 793 * will get this call through intel_pmu_cpu_starting(). 794 */ 795 init_debug_store_on_cpu(cpu); 796 } 797 } 798 } 799 800 /* 801 * BTS 802 */ 803 804 struct event_constraint bts_constraint = 805 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0); 806 intel_pmu_enable_bts(u64 config)807 void intel_pmu_enable_bts(u64 config) 808 { 809 unsigned long debugctlmsr; 810 811 debugctlmsr = get_debugctlmsr(); 812 813 debugctlmsr |= DEBUGCTLMSR_TR; 814 debugctlmsr |= DEBUGCTLMSR_BTS; 815 if (config & ARCH_PERFMON_EVENTSEL_INT) 816 debugctlmsr |= DEBUGCTLMSR_BTINT; 817 818 if (!(config & ARCH_PERFMON_EVENTSEL_OS)) 819 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS; 820 821 if (!(config & ARCH_PERFMON_EVENTSEL_USR)) 822 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR; 823 824 update_debugctlmsr(debugctlmsr); 825 } 826 intel_pmu_disable_bts(void)827 void intel_pmu_disable_bts(void) 828 { 829 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 830 unsigned long debugctlmsr; 831 832 if (!cpuc->ds) 833 return; 834 835 debugctlmsr = get_debugctlmsr(); 836 837 debugctlmsr &= 838 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT | 839 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR); 840 841 update_debugctlmsr(debugctlmsr); 842 } 843 intel_pmu_drain_bts_buffer(void)844 int intel_pmu_drain_bts_buffer(void) 845 { 846 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 847 struct debug_store *ds = cpuc->ds; 848 struct bts_record { 849 u64 from; 850 u64 to; 851 u64 flags; 852 }; 853 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 854 struct bts_record *at, *base, *top; 855 struct perf_output_handle handle; 856 struct perf_event_header header; 857 struct perf_sample_data data; 858 unsigned long skip = 0; 859 struct pt_regs regs; 860 861 if (!event) 862 return 0; 863 864 if (!x86_pmu.bts_active) 865 return 0; 866 867 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; 868 top = (struct bts_record *)(unsigned long)ds->bts_index; 869 870 if (top <= base) 871 return 0; 872 873 memset(®s, 0, sizeof(regs)); 874 875 ds->bts_index = ds->bts_buffer_base; 876 877 perf_sample_data_init(&data, 0, event->hw.last_period); 878 879 /* 880 * BTS leaks kernel addresses in branches across the cpl boundary, 881 * such as traps or system calls, so unless the user is asking for 882 * kernel tracing (and right now it's not possible), we'd need to 883 * filter them out. But first we need to count how many of those we 884 * have in the current batch. This is an extra O(n) pass, however, 885 * it's much faster than the other one especially considering that 886 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the 887 * alloc_bts_buffer()). 888 */ 889 for (at = base; at < top; at++) { 890 /* 891 * Note that right now *this* BTS code only works if 892 * attr::exclude_kernel is set, but let's keep this extra 893 * check here in case that changes. 894 */ 895 if (event->attr.exclude_kernel && 896 (kernel_ip(at->from) || kernel_ip(at->to))) 897 skip++; 898 } 899 900 /* 901 * Prepare a generic sample, i.e. fill in the invariant fields. 902 * We will overwrite the from and to address before we output 903 * the sample. 904 */ 905 rcu_read_lock(); 906 perf_prepare_sample(&data, event, ®s); 907 perf_prepare_header(&header, &data, event, ®s); 908 909 if (perf_output_begin(&handle, &data, event, 910 header.size * (top - base - skip))) 911 goto unlock; 912 913 for (at = base; at < top; at++) { 914 /* Filter out any records that contain kernel addresses. */ 915 if (event->attr.exclude_kernel && 916 (kernel_ip(at->from) || kernel_ip(at->to))) 917 continue; 918 919 data.ip = at->from; 920 data.addr = at->to; 921 922 perf_output_sample(&handle, &header, &data, event); 923 } 924 925 perf_output_end(&handle); 926 927 /* There's new data available. */ 928 event->hw.interrupts++; 929 event->pending_kill = POLL_IN; 930 unlock: 931 rcu_read_unlock(); 932 return 1; 933 } 934 intel_pmu_drain_pebs_buffer(void)935 static inline void intel_pmu_drain_pebs_buffer(void) 936 { 937 struct perf_sample_data data; 938 939 x86_pmu.drain_pebs(NULL, &data); 940 } 941 942 /* 943 * PEBS 944 */ 945 struct event_constraint intel_core2_pebs_event_constraints[] = { 946 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 947 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ 948 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ 949 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ 950 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 951 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 952 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01), 953 EVENT_CONSTRAINT_END 954 }; 955 956 struct event_constraint intel_atom_pebs_event_constraints[] = { 957 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 958 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ 959 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 960 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 961 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01), 962 /* Allow all events as PEBS with no flags */ 963 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 964 EVENT_CONSTRAINT_END 965 }; 966 967 struct event_constraint intel_slm_pebs_event_constraints[] = { 968 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 969 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1), 970 /* Allow all events as PEBS with no flags */ 971 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 972 EVENT_CONSTRAINT_END 973 }; 974 975 struct event_constraint intel_glm_pebs_event_constraints[] = { 976 /* Allow all events as PEBS with no flags */ 977 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 978 EVENT_CONSTRAINT_END 979 }; 980 981 struct event_constraint intel_grt_pebs_event_constraints[] = { 982 /* Allow all events as PEBS with no flags */ 983 INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3), 984 INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf), 985 EVENT_CONSTRAINT_END 986 }; 987 988 struct event_constraint intel_nehalem_pebs_event_constraints[] = { 989 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 990 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 991 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 992 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */ 993 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 994 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 995 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ 996 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 997 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 998 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 999 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 1000 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 1001 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f), 1002 EVENT_CONSTRAINT_END 1003 }; 1004 1005 struct event_constraint intel_westmere_pebs_event_constraints[] = { 1006 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 1007 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 1008 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 1009 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */ 1010 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 1011 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 1012 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ 1013 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 1014 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 1015 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 1016 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 1017 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 1018 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f), 1019 EVENT_CONSTRAINT_END 1020 }; 1021 1022 struct event_constraint intel_snb_pebs_event_constraints[] = { 1023 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 1024 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 1025 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 1026 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 1027 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf), 1028 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 1029 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 1030 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 1031 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 1032 /* Allow all events as PEBS with no flags */ 1033 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1034 EVENT_CONSTRAINT_END 1035 }; 1036 1037 struct event_constraint intel_ivb_pebs_event_constraints[] = { 1038 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 1039 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 1040 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 1041 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 1042 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf), 1043 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 1044 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2), 1045 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 1046 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 1047 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 1048 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 1049 /* Allow all events as PEBS with no flags */ 1050 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1051 EVENT_CONSTRAINT_END 1052 }; 1053 1054 struct event_constraint intel_hsw_pebs_event_constraints[] = { 1055 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 1056 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 1057 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 1058 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf), 1059 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 1060 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2), 1061 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 1062 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 1063 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 1064 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 1065 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 1066 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 1067 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 1068 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 1069 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 1070 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 1071 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 1072 /* Allow all events as PEBS with no flags */ 1073 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1074 EVENT_CONSTRAINT_END 1075 }; 1076 1077 struct event_constraint intel_bdw_pebs_event_constraints[] = { 1078 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 1079 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 1080 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 1081 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf), 1082 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 1083 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2), 1084 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 1085 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 1086 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 1087 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 1088 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 1089 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 1090 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 1091 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 1092 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 1093 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 1094 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 1095 /* Allow all events as PEBS with no flags */ 1096 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1097 EVENT_CONSTRAINT_END 1098 }; 1099 1100 1101 struct event_constraint intel_skl_pebs_event_constraints[] = { 1102 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 1103 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 1104 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2), 1105 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */ 1106 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f), 1107 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */ 1108 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 1109 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 1110 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 1111 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */ 1112 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 1113 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 1114 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 1115 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 1116 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 1117 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 1118 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */ 1119 /* Allow all events as PEBS with no flags */ 1120 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 1121 EVENT_CONSTRAINT_END 1122 }; 1123 1124 struct event_constraint intel_icl_pebs_event_constraints[] = { 1125 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */ 1126 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */ 1127 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */ 1128 1129 INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 1130 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 1131 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 1132 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 1133 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 1134 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 1135 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 1136 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 1137 1138 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */ 1139 1140 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 1141 1142 /* 1143 * Everything else is handled by PMU_FL_PEBS_ALL, because we 1144 * need the full constraints from the main table. 1145 */ 1146 1147 EVENT_CONSTRAINT_END 1148 }; 1149 1150 struct event_constraint intel_glc_pebs_event_constraints[] = { 1151 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */ 1152 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), 1153 1154 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe), 1155 INTEL_PLD_CONSTRAINT(0x1cd, 0xfe), 1156 INTEL_PSD_CONSTRAINT(0x2cd, 0x1), 1157 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 1158 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 1159 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 1160 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 1161 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 1162 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 1163 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 1164 1165 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), 1166 1167 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), 1168 1169 /* 1170 * Everything else is handled by PMU_FL_PEBS_ALL, because we 1171 * need the full constraints from the main table. 1172 */ 1173 1174 EVENT_CONSTRAINT_END 1175 }; 1176 1177 struct event_constraint intel_lnc_pebs_event_constraints[] = { 1178 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */ 1179 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), 1180 1181 INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3ff), 1182 INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3), 1183 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 1184 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 1185 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 1186 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 1187 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 1188 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 1189 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 1190 1191 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), 1192 1193 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), 1194 1195 /* 1196 * Everything else is handled by PMU_FL_PEBS_ALL, because we 1197 * need the full constraints from the main table. 1198 */ 1199 1200 EVENT_CONSTRAINT_END 1201 }; 1202 intel_pebs_constraints(struct perf_event * event)1203 struct event_constraint *intel_pebs_constraints(struct perf_event *event) 1204 { 1205 struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints); 1206 struct event_constraint *c; 1207 1208 if (!event->attr.precise_ip) 1209 return NULL; 1210 1211 if (pebs_constraints) { 1212 for_each_event_constraint(c, pebs_constraints) { 1213 if (constraint_match(c, event->hw.config)) { 1214 event->hw.flags |= c->flags; 1215 return c; 1216 } 1217 } 1218 } 1219 1220 /* 1221 * Extended PEBS support 1222 * Makes the PEBS code search the normal constraints. 1223 */ 1224 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 1225 return NULL; 1226 1227 return &emptyconstraint; 1228 } 1229 1230 /* 1231 * We need the sched_task callback even for per-cpu events when we use 1232 * the large interrupt threshold, such that we can provide PID and TID 1233 * to PEBS samples. 1234 */ pebs_needs_sched_cb(struct cpu_hw_events * cpuc)1235 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc) 1236 { 1237 if (cpuc->n_pebs == cpuc->n_pebs_via_pt) 1238 return false; 1239 1240 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); 1241 } 1242 intel_pmu_pebs_sched_task(struct perf_event_pmu_context * pmu_ctx,bool sched_in)1243 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in) 1244 { 1245 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1246 1247 if (!sched_in && pebs_needs_sched_cb(cpuc)) 1248 intel_pmu_drain_pebs_buffer(); 1249 } 1250 pebs_update_threshold(struct cpu_hw_events * cpuc)1251 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc) 1252 { 1253 struct debug_store *ds = cpuc->ds; 1254 int max_pebs_events = intel_pmu_max_num_pebs(cpuc->pmu); 1255 u64 threshold; 1256 int reserved; 1257 1258 if (cpuc->n_pebs_via_pt) 1259 return; 1260 1261 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 1262 reserved = max_pebs_events + x86_pmu_max_num_counters_fixed(cpuc->pmu); 1263 else 1264 reserved = max_pebs_events; 1265 1266 if (cpuc->n_pebs == cpuc->n_large_pebs) { 1267 threshold = ds->pebs_absolute_maximum - 1268 reserved * cpuc->pebs_record_size; 1269 } else { 1270 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size; 1271 } 1272 1273 ds->pebs_interrupt_threshold = threshold; 1274 } 1275 adaptive_pebs_record_size_update(void)1276 static void adaptive_pebs_record_size_update(void) 1277 { 1278 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1279 u64 pebs_data_cfg = cpuc->pebs_data_cfg; 1280 int sz = sizeof(struct pebs_basic); 1281 1282 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO) 1283 sz += sizeof(struct pebs_meminfo); 1284 if (pebs_data_cfg & PEBS_DATACFG_GP) 1285 sz += sizeof(struct pebs_gprs); 1286 if (pebs_data_cfg & PEBS_DATACFG_XMMS) 1287 sz += sizeof(struct pebs_xmm); 1288 if (pebs_data_cfg & PEBS_DATACFG_LBRS) 1289 sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry); 1290 1291 cpuc->pebs_record_size = sz; 1292 } 1293 1294 #define PERF_PEBS_MEMINFO_TYPE (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC | \ 1295 PERF_SAMPLE_PHYS_ADDR | \ 1296 PERF_SAMPLE_WEIGHT_TYPE | \ 1297 PERF_SAMPLE_TRANSACTION | \ 1298 PERF_SAMPLE_DATA_PAGE_SIZE) 1299 pebs_update_adaptive_cfg(struct perf_event * event)1300 static u64 pebs_update_adaptive_cfg(struct perf_event *event) 1301 { 1302 struct perf_event_attr *attr = &event->attr; 1303 u64 sample_type = attr->sample_type; 1304 u64 pebs_data_cfg = 0; 1305 bool gprs, tsx_weight; 1306 1307 if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) && 1308 attr->precise_ip > 1) 1309 return pebs_data_cfg; 1310 1311 if (sample_type & PERF_PEBS_MEMINFO_TYPE) 1312 pebs_data_cfg |= PEBS_DATACFG_MEMINFO; 1313 1314 /* 1315 * We need GPRs when: 1316 * + user requested them 1317 * + precise_ip < 2 for the non event IP 1318 * + For RTM TSX weight we need GPRs for the abort code. 1319 */ 1320 gprs = (sample_type & PERF_SAMPLE_REGS_INTR) && 1321 (attr->sample_regs_intr & PEBS_GP_REGS); 1322 1323 tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 1324 ((attr->config & INTEL_ARCH_EVENT_MASK) == 1325 x86_pmu.rtm_abort_event); 1326 1327 if (gprs || (attr->precise_ip < 2) || tsx_weight) 1328 pebs_data_cfg |= PEBS_DATACFG_GP; 1329 1330 if ((sample_type & PERF_SAMPLE_REGS_INTR) && 1331 (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK)) 1332 pebs_data_cfg |= PEBS_DATACFG_XMMS; 1333 1334 if (sample_type & PERF_SAMPLE_BRANCH_STACK) { 1335 /* 1336 * For now always log all LBRs. Could configure this 1337 * later. 1338 */ 1339 pebs_data_cfg |= PEBS_DATACFG_LBRS | 1340 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT); 1341 } 1342 1343 return pebs_data_cfg; 1344 } 1345 1346 static void pebs_update_state(bool needed_cb,struct cpu_hw_events * cpuc,struct perf_event * event,bool add)1347 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, 1348 struct perf_event *event, bool add) 1349 { 1350 struct pmu *pmu = event->pmu; 1351 1352 /* 1353 * Make sure we get updated with the first PEBS event. 1354 * During removal, ->pebs_data_cfg is still valid for 1355 * the last PEBS event. Don't clear it. 1356 */ 1357 if ((cpuc->n_pebs == 1) && add) 1358 cpuc->pebs_data_cfg = PEBS_UPDATE_DS_SW; 1359 1360 if (needed_cb != pebs_needs_sched_cb(cpuc)) { 1361 if (!needed_cb) 1362 perf_sched_cb_inc(pmu); 1363 else 1364 perf_sched_cb_dec(pmu); 1365 1366 cpuc->pebs_data_cfg |= PEBS_UPDATE_DS_SW; 1367 } 1368 1369 /* 1370 * The PEBS record doesn't shrink on pmu::del(). Doing so would require 1371 * iterating all remaining PEBS events to reconstruct the config. 1372 */ 1373 if (x86_pmu.intel_cap.pebs_baseline && add) { 1374 u64 pebs_data_cfg; 1375 1376 pebs_data_cfg = pebs_update_adaptive_cfg(event); 1377 /* 1378 * Be sure to update the thresholds when we change the record. 1379 */ 1380 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) 1381 cpuc->pebs_data_cfg |= pebs_data_cfg | PEBS_UPDATE_DS_SW; 1382 } 1383 } 1384 intel_pmu_pebs_add(struct perf_event * event)1385 void intel_pmu_pebs_add(struct perf_event *event) 1386 { 1387 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1388 struct hw_perf_event *hwc = &event->hw; 1389 bool needed_cb = pebs_needs_sched_cb(cpuc); 1390 1391 cpuc->n_pebs++; 1392 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 1393 cpuc->n_large_pebs++; 1394 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) 1395 cpuc->n_pebs_via_pt++; 1396 1397 pebs_update_state(needed_cb, cpuc, event, true); 1398 } 1399 intel_pmu_pebs_via_pt_disable(struct perf_event * event)1400 static void intel_pmu_pebs_via_pt_disable(struct perf_event *event) 1401 { 1402 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1403 1404 if (!is_pebs_pt(event)) 1405 return; 1406 1407 if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK)) 1408 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK; 1409 } 1410 intel_pmu_pebs_via_pt_enable(struct perf_event * event)1411 static void intel_pmu_pebs_via_pt_enable(struct perf_event *event) 1412 { 1413 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1414 struct hw_perf_event *hwc = &event->hw; 1415 struct debug_store *ds = cpuc->ds; 1416 u64 value = ds->pebs_event_reset[hwc->idx]; 1417 u32 base = MSR_RELOAD_PMC0; 1418 unsigned int idx = hwc->idx; 1419 1420 if (!is_pebs_pt(event)) 1421 return; 1422 1423 if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) 1424 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD; 1425 1426 cpuc->pebs_enabled |= PEBS_OUTPUT_PT; 1427 1428 if (hwc->idx >= INTEL_PMC_IDX_FIXED) { 1429 base = MSR_RELOAD_FIXED_CTR0; 1430 idx = hwc->idx - INTEL_PMC_IDX_FIXED; 1431 if (x86_pmu.intel_cap.pebs_format < 5) 1432 value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx]; 1433 else 1434 value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx]; 1435 } 1436 wrmsrl(base + idx, value); 1437 } 1438 intel_pmu_drain_large_pebs(struct cpu_hw_events * cpuc)1439 static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc) 1440 { 1441 if (cpuc->n_pebs == cpuc->n_large_pebs && 1442 cpuc->n_pebs != cpuc->n_pebs_via_pt) 1443 intel_pmu_drain_pebs_buffer(); 1444 } 1445 intel_pmu_pebs_enable(struct perf_event * event)1446 void intel_pmu_pebs_enable(struct perf_event *event) 1447 { 1448 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1449 u64 pebs_data_cfg = cpuc->pebs_data_cfg & ~PEBS_UPDATE_DS_SW; 1450 struct hw_perf_event *hwc = &event->hw; 1451 struct debug_store *ds = cpuc->ds; 1452 unsigned int idx = hwc->idx; 1453 1454 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; 1455 1456 cpuc->pebs_enabled |= 1ULL << hwc->idx; 1457 1458 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5)) 1459 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); 1460 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 1461 cpuc->pebs_enabled |= 1ULL << 63; 1462 1463 if (x86_pmu.intel_cap.pebs_baseline) { 1464 hwc->config |= ICL_EVENTSEL_ADAPTIVE; 1465 if (pebs_data_cfg != cpuc->active_pebs_data_cfg) { 1466 /* 1467 * drain_pebs() assumes uniform record size; 1468 * hence we need to drain when changing said 1469 * size. 1470 */ 1471 intel_pmu_drain_large_pebs(cpuc); 1472 adaptive_pebs_record_size_update(); 1473 wrmsrl(MSR_PEBS_DATA_CFG, pebs_data_cfg); 1474 cpuc->active_pebs_data_cfg = pebs_data_cfg; 1475 } 1476 } 1477 if (cpuc->pebs_data_cfg & PEBS_UPDATE_DS_SW) { 1478 cpuc->pebs_data_cfg = pebs_data_cfg; 1479 pebs_update_threshold(cpuc); 1480 } 1481 1482 if (idx >= INTEL_PMC_IDX_FIXED) { 1483 if (x86_pmu.intel_cap.pebs_format < 5) 1484 idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED); 1485 else 1486 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED); 1487 } 1488 1489 /* 1490 * Use auto-reload if possible to save a MSR write in the PMI. 1491 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD. 1492 */ 1493 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 1494 ds->pebs_event_reset[idx] = 1495 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; 1496 } else { 1497 ds->pebs_event_reset[idx] = 0; 1498 } 1499 1500 intel_pmu_pebs_via_pt_enable(event); 1501 } 1502 intel_pmu_pebs_del(struct perf_event * event)1503 void intel_pmu_pebs_del(struct perf_event *event) 1504 { 1505 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1506 struct hw_perf_event *hwc = &event->hw; 1507 bool needed_cb = pebs_needs_sched_cb(cpuc); 1508 1509 cpuc->n_pebs--; 1510 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 1511 cpuc->n_large_pebs--; 1512 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) 1513 cpuc->n_pebs_via_pt--; 1514 1515 pebs_update_state(needed_cb, cpuc, event, false); 1516 } 1517 intel_pmu_pebs_disable(struct perf_event * event)1518 void intel_pmu_pebs_disable(struct perf_event *event) 1519 { 1520 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1521 struct hw_perf_event *hwc = &event->hw; 1522 1523 intel_pmu_drain_large_pebs(cpuc); 1524 1525 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); 1526 1527 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && 1528 (x86_pmu.version < 5)) 1529 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); 1530 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 1531 cpuc->pebs_enabled &= ~(1ULL << 63); 1532 1533 intel_pmu_pebs_via_pt_disable(event); 1534 1535 if (cpuc->enabled) 1536 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1537 1538 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; 1539 } 1540 intel_pmu_pebs_enable_all(void)1541 void intel_pmu_pebs_enable_all(void) 1542 { 1543 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1544 1545 if (cpuc->pebs_enabled) 1546 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1547 } 1548 intel_pmu_pebs_disable_all(void)1549 void intel_pmu_pebs_disable_all(void) 1550 { 1551 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1552 1553 if (cpuc->pebs_enabled) 1554 __intel_pmu_pebs_disable_all(); 1555 } 1556 intel_pmu_pebs_fixup_ip(struct pt_regs * regs)1557 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) 1558 { 1559 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1560 unsigned long from = cpuc->lbr_entries[0].from; 1561 unsigned long old_to, to = cpuc->lbr_entries[0].to; 1562 unsigned long ip = regs->ip; 1563 int is_64bit = 0; 1564 void *kaddr; 1565 int size; 1566 1567 /* 1568 * We don't need to fixup if the PEBS assist is fault like 1569 */ 1570 if (!x86_pmu.intel_cap.pebs_trap) 1571 return 1; 1572 1573 /* 1574 * No LBR entry, no basic block, no rewinding 1575 */ 1576 if (!cpuc->lbr_stack.nr || !from || !to) 1577 return 0; 1578 1579 /* 1580 * Basic blocks should never cross user/kernel boundaries 1581 */ 1582 if (kernel_ip(ip) != kernel_ip(to)) 1583 return 0; 1584 1585 /* 1586 * unsigned math, either ip is before the start (impossible) or 1587 * the basic block is larger than 1 page (sanity) 1588 */ 1589 if ((ip - to) > PEBS_FIXUP_SIZE) 1590 return 0; 1591 1592 /* 1593 * We sampled a branch insn, rewind using the LBR stack 1594 */ 1595 if (ip == to) { 1596 set_linear_ip(regs, from); 1597 return 1; 1598 } 1599 1600 size = ip - to; 1601 if (!kernel_ip(ip)) { 1602 int bytes; 1603 u8 *buf = this_cpu_read(insn_buffer); 1604 1605 /* 'size' must fit our buffer, see above */ 1606 bytes = copy_from_user_nmi(buf, (void __user *)to, size); 1607 if (bytes != 0) 1608 return 0; 1609 1610 kaddr = buf; 1611 } else { 1612 kaddr = (void *)to; 1613 } 1614 1615 do { 1616 struct insn insn; 1617 1618 old_to = to; 1619 1620 #ifdef CONFIG_X86_64 1621 is_64bit = kernel_ip(to) || any_64bit_mode(regs); 1622 #endif 1623 insn_init(&insn, kaddr, size, is_64bit); 1624 1625 /* 1626 * Make sure there was not a problem decoding the instruction. 1627 * This is doubly important because we have an infinite loop if 1628 * insn.length=0. 1629 */ 1630 if (insn_get_length(&insn)) 1631 break; 1632 1633 to += insn.length; 1634 kaddr += insn.length; 1635 size -= insn.length; 1636 } while (to < ip); 1637 1638 if (to == ip) { 1639 set_linear_ip(regs, old_to); 1640 return 1; 1641 } 1642 1643 /* 1644 * Even though we decoded the basic block, the instruction stream 1645 * never matched the given IP, either the TO or the IP got corrupted. 1646 */ 1647 return 0; 1648 } 1649 intel_get_tsx_weight(u64 tsx_tuning)1650 static inline u64 intel_get_tsx_weight(u64 tsx_tuning) 1651 { 1652 if (tsx_tuning) { 1653 union hsw_tsx_tuning tsx = { .value = tsx_tuning }; 1654 return tsx.cycles_last_block; 1655 } 1656 return 0; 1657 } 1658 intel_get_tsx_transaction(u64 tsx_tuning,u64 ax)1659 static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax) 1660 { 1661 u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; 1662 1663 /* For RTM XABORTs also log the abort code from AX */ 1664 if ((txn & PERF_TXN_TRANSACTION) && (ax & 1)) 1665 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; 1666 return txn; 1667 } 1668 get_pebs_status(void * n)1669 static inline u64 get_pebs_status(void *n) 1670 { 1671 if (x86_pmu.intel_cap.pebs_format < 4) 1672 return ((struct pebs_record_nhm *)n)->status; 1673 return ((struct pebs_basic *)n)->applicable_counters; 1674 } 1675 1676 #define PERF_X86_EVENT_PEBS_HSW_PREC \ 1677 (PERF_X86_EVENT_PEBS_ST_HSW | \ 1678 PERF_X86_EVENT_PEBS_LD_HSW | \ 1679 PERF_X86_EVENT_PEBS_NA_HSW) 1680 get_data_src(struct perf_event * event,u64 aux)1681 static u64 get_data_src(struct perf_event *event, u64 aux) 1682 { 1683 u64 val = PERF_MEM_NA; 1684 int fl = event->hw.flags; 1685 bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC); 1686 1687 if (fl & PERF_X86_EVENT_PEBS_LDLAT) 1688 val = load_latency_data(event, aux); 1689 else if (fl & PERF_X86_EVENT_PEBS_STLAT) 1690 val = store_latency_data(event, aux); 1691 else if (fl & PERF_X86_EVENT_PEBS_LAT_HYBRID) 1692 val = x86_pmu.pebs_latency_data(event, aux); 1693 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC)) 1694 val = precise_datala_hsw(event, aux); 1695 else if (fst) 1696 val = precise_store_data(aux); 1697 return val; 1698 } 1699 setup_pebs_time(struct perf_event * event,struct perf_sample_data * data,u64 tsc)1700 static void setup_pebs_time(struct perf_event *event, 1701 struct perf_sample_data *data, 1702 u64 tsc) 1703 { 1704 /* Converting to a user-defined clock is not supported yet. */ 1705 if (event->attr.use_clockid != 0) 1706 return; 1707 1708 /* 1709 * Doesn't support the conversion when the TSC is unstable. 1710 * The TSC unstable case is a corner case and very unlikely to 1711 * happen. If it happens, the TSC in a PEBS record will be 1712 * dropped and fall back to perf_event_clock(). 1713 */ 1714 if (!using_native_sched_clock() || !sched_clock_stable()) 1715 return; 1716 1717 data->time = native_sched_clock_from_tsc(tsc) + __sched_clock_offset; 1718 data->sample_flags |= PERF_SAMPLE_TIME; 1719 } 1720 1721 #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \ 1722 PERF_SAMPLE_PHYS_ADDR | \ 1723 PERF_SAMPLE_DATA_PAGE_SIZE) 1724 setup_pebs_fixed_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)1725 static void setup_pebs_fixed_sample_data(struct perf_event *event, 1726 struct pt_regs *iregs, void *__pebs, 1727 struct perf_sample_data *data, 1728 struct pt_regs *regs) 1729 { 1730 /* 1731 * We cast to the biggest pebs_record but are careful not to 1732 * unconditionally access the 'extra' entries. 1733 */ 1734 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1735 struct pebs_record_skl *pebs = __pebs; 1736 u64 sample_type; 1737 int fll; 1738 1739 if (pebs == NULL) 1740 return; 1741 1742 sample_type = event->attr.sample_type; 1743 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT; 1744 1745 perf_sample_data_init(data, 0, event->hw.last_period); 1746 1747 data->period = event->hw.last_period; 1748 1749 /* 1750 * Use latency for weight (only avail with PEBS-LL) 1751 */ 1752 if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE)) { 1753 data->weight.full = pebs->lat; 1754 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; 1755 } 1756 1757 /* 1758 * data.data_src encodes the data source 1759 */ 1760 if (sample_type & PERF_SAMPLE_DATA_SRC) { 1761 data->data_src.val = get_data_src(event, pebs->dse); 1762 data->sample_flags |= PERF_SAMPLE_DATA_SRC; 1763 } 1764 1765 /* 1766 * We must however always use iregs for the unwinder to stay sane; the 1767 * record BP,SP,IP can point into thin air when the record is from a 1768 * previous PMI context or an (I)RET happened between the record and 1769 * PMI. 1770 */ 1771 if (sample_type & PERF_SAMPLE_CALLCHAIN) 1772 perf_sample_save_callchain(data, event, iregs); 1773 1774 /* 1775 * We use the interrupt regs as a base because the PEBS record does not 1776 * contain a full regs set, specifically it seems to lack segment 1777 * descriptors, which get used by things like user_mode(). 1778 * 1779 * In the simple case fix up only the IP for PERF_SAMPLE_IP. 1780 */ 1781 *regs = *iregs; 1782 1783 /* 1784 * Initialize regs_>flags from PEBS, 1785 * Clear exact bit (which uses x86 EFLAGS Reserved bit 3), 1786 * i.e., do not rely on it being zero: 1787 */ 1788 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT; 1789 1790 if (sample_type & PERF_SAMPLE_REGS_INTR) { 1791 regs->ax = pebs->ax; 1792 regs->bx = pebs->bx; 1793 regs->cx = pebs->cx; 1794 regs->dx = pebs->dx; 1795 regs->si = pebs->si; 1796 regs->di = pebs->di; 1797 1798 regs->bp = pebs->bp; 1799 regs->sp = pebs->sp; 1800 1801 #ifndef CONFIG_X86_32 1802 regs->r8 = pebs->r8; 1803 regs->r9 = pebs->r9; 1804 regs->r10 = pebs->r10; 1805 regs->r11 = pebs->r11; 1806 regs->r12 = pebs->r12; 1807 regs->r13 = pebs->r13; 1808 regs->r14 = pebs->r14; 1809 regs->r15 = pebs->r15; 1810 #endif 1811 } 1812 1813 if (event->attr.precise_ip > 1) { 1814 /* 1815 * Haswell and later processors have an 'eventing IP' 1816 * (real IP) which fixes the off-by-1 skid in hardware. 1817 * Use it when precise_ip >= 2 : 1818 */ 1819 if (x86_pmu.intel_cap.pebs_format >= 2) { 1820 set_linear_ip(regs, pebs->real_ip); 1821 regs->flags |= PERF_EFLAGS_EXACT; 1822 } else { 1823 /* Otherwise, use PEBS off-by-1 IP: */ 1824 set_linear_ip(regs, pebs->ip); 1825 1826 /* 1827 * With precise_ip >= 2, try to fix up the off-by-1 IP 1828 * using the LBR. If successful, the fixup function 1829 * corrects regs->ip and calls set_linear_ip() on regs: 1830 */ 1831 if (intel_pmu_pebs_fixup_ip(regs)) 1832 regs->flags |= PERF_EFLAGS_EXACT; 1833 } 1834 } else { 1835 /* 1836 * When precise_ip == 1, return the PEBS off-by-1 IP, 1837 * no fixup attempted: 1838 */ 1839 set_linear_ip(regs, pebs->ip); 1840 } 1841 1842 1843 if ((sample_type & PERF_SAMPLE_ADDR_TYPE) && 1844 x86_pmu.intel_cap.pebs_format >= 1) { 1845 data->addr = pebs->dla; 1846 data->sample_flags |= PERF_SAMPLE_ADDR; 1847 } 1848 1849 if (x86_pmu.intel_cap.pebs_format >= 2) { 1850 /* Only set the TSX weight when no memory weight. */ 1851 if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll) { 1852 data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning); 1853 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; 1854 } 1855 if (sample_type & PERF_SAMPLE_TRANSACTION) { 1856 data->txn = intel_get_tsx_transaction(pebs->tsx_tuning, 1857 pebs->ax); 1858 data->sample_flags |= PERF_SAMPLE_TRANSACTION; 1859 } 1860 } 1861 1862 /* 1863 * v3 supplies an accurate time stamp, so we use that 1864 * for the time stamp. 1865 * 1866 * We can only do this for the default trace clock. 1867 */ 1868 if (x86_pmu.intel_cap.pebs_format >= 3) 1869 setup_pebs_time(event, data, pebs->tsc); 1870 1871 if (has_branch_stack(event)) 1872 perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL); 1873 } 1874 adaptive_pebs_save_regs(struct pt_regs * regs,struct pebs_gprs * gprs)1875 static void adaptive_pebs_save_regs(struct pt_regs *regs, 1876 struct pebs_gprs *gprs) 1877 { 1878 regs->ax = gprs->ax; 1879 regs->bx = gprs->bx; 1880 regs->cx = gprs->cx; 1881 regs->dx = gprs->dx; 1882 regs->si = gprs->si; 1883 regs->di = gprs->di; 1884 regs->bp = gprs->bp; 1885 regs->sp = gprs->sp; 1886 #ifndef CONFIG_X86_32 1887 regs->r8 = gprs->r8; 1888 regs->r9 = gprs->r9; 1889 regs->r10 = gprs->r10; 1890 regs->r11 = gprs->r11; 1891 regs->r12 = gprs->r12; 1892 regs->r13 = gprs->r13; 1893 regs->r14 = gprs->r14; 1894 regs->r15 = gprs->r15; 1895 #endif 1896 } 1897 1898 #define PEBS_LATENCY_MASK 0xffff 1899 #define PEBS_CACHE_LATENCY_OFFSET 32 1900 #define PEBS_RETIRE_LATENCY_OFFSET 32 1901 1902 /* 1903 * With adaptive PEBS the layout depends on what fields are configured. 1904 */ 1905 setup_pebs_adaptive_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)1906 static void setup_pebs_adaptive_sample_data(struct perf_event *event, 1907 struct pt_regs *iregs, void *__pebs, 1908 struct perf_sample_data *data, 1909 struct pt_regs *regs) 1910 { 1911 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1912 struct pebs_basic *basic = __pebs; 1913 void *next_record = basic + 1; 1914 u64 sample_type; 1915 u64 format_size; 1916 struct pebs_meminfo *meminfo = NULL; 1917 struct pebs_gprs *gprs = NULL; 1918 struct x86_perf_regs *perf_regs; 1919 1920 if (basic == NULL) 1921 return; 1922 1923 perf_regs = container_of(regs, struct x86_perf_regs, regs); 1924 perf_regs->xmm_regs = NULL; 1925 1926 sample_type = event->attr.sample_type; 1927 format_size = basic->format_size; 1928 perf_sample_data_init(data, 0, event->hw.last_period); 1929 data->period = event->hw.last_period; 1930 1931 setup_pebs_time(event, data, basic->tsc); 1932 1933 /* 1934 * We must however always use iregs for the unwinder to stay sane; the 1935 * record BP,SP,IP can point into thin air when the record is from a 1936 * previous PMI context or an (I)RET happened between the record and 1937 * PMI. 1938 */ 1939 if (sample_type & PERF_SAMPLE_CALLCHAIN) 1940 perf_sample_save_callchain(data, event, iregs); 1941 1942 *regs = *iregs; 1943 /* The ip in basic is EventingIP */ 1944 set_linear_ip(regs, basic->ip); 1945 regs->flags = PERF_EFLAGS_EXACT; 1946 1947 if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) { 1948 if (x86_pmu.flags & PMU_FL_RETIRE_LATENCY) 1949 data->weight.var3_w = format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEBS_LATENCY_MASK; 1950 else 1951 data->weight.var3_w = 0; 1952 } 1953 1954 /* 1955 * The record for MEMINFO is in front of GP 1956 * But PERF_SAMPLE_TRANSACTION needs gprs->ax. 1957 * Save the pointer here but process later. 1958 */ 1959 if (format_size & PEBS_DATACFG_MEMINFO) { 1960 meminfo = next_record; 1961 next_record = meminfo + 1; 1962 } 1963 1964 if (format_size & PEBS_DATACFG_GP) { 1965 gprs = next_record; 1966 next_record = gprs + 1; 1967 1968 if (event->attr.precise_ip < 2) { 1969 set_linear_ip(regs, gprs->ip); 1970 regs->flags &= ~PERF_EFLAGS_EXACT; 1971 } 1972 1973 if (sample_type & PERF_SAMPLE_REGS_INTR) 1974 adaptive_pebs_save_regs(regs, gprs); 1975 } 1976 1977 if (format_size & PEBS_DATACFG_MEMINFO) { 1978 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) { 1979 u64 weight = meminfo->latency; 1980 1981 if (x86_pmu.flags & PMU_FL_INSTR_LATENCY) { 1982 data->weight.var2_w = weight & PEBS_LATENCY_MASK; 1983 weight >>= PEBS_CACHE_LATENCY_OFFSET; 1984 } 1985 1986 /* 1987 * Although meminfo::latency is defined as a u64, 1988 * only the lower 32 bits include the valid data 1989 * in practice on Ice Lake and earlier platforms. 1990 */ 1991 if (sample_type & PERF_SAMPLE_WEIGHT) { 1992 data->weight.full = weight ?: 1993 intel_get_tsx_weight(meminfo->tsx_tuning); 1994 } else { 1995 data->weight.var1_dw = (u32)(weight & PEBS_LATENCY_MASK) ?: 1996 intel_get_tsx_weight(meminfo->tsx_tuning); 1997 } 1998 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; 1999 } 2000 2001 if (sample_type & PERF_SAMPLE_DATA_SRC) { 2002 data->data_src.val = get_data_src(event, meminfo->aux); 2003 data->sample_flags |= PERF_SAMPLE_DATA_SRC; 2004 } 2005 2006 if (sample_type & PERF_SAMPLE_ADDR_TYPE) { 2007 data->addr = meminfo->address; 2008 data->sample_flags |= PERF_SAMPLE_ADDR; 2009 } 2010 2011 if (sample_type & PERF_SAMPLE_TRANSACTION) { 2012 data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning, 2013 gprs ? gprs->ax : 0); 2014 data->sample_flags |= PERF_SAMPLE_TRANSACTION; 2015 } 2016 } 2017 2018 if (format_size & PEBS_DATACFG_XMMS) { 2019 struct pebs_xmm *xmm = next_record; 2020 2021 next_record = xmm + 1; 2022 perf_regs->xmm_regs = xmm->xmm; 2023 } 2024 2025 if (format_size & PEBS_DATACFG_LBRS) { 2026 struct lbr_entry *lbr = next_record; 2027 int num_lbr = ((format_size >> PEBS_DATACFG_LBR_SHIFT) 2028 & 0xff) + 1; 2029 next_record = next_record + num_lbr * sizeof(struct lbr_entry); 2030 2031 if (has_branch_stack(event)) { 2032 intel_pmu_store_pebs_lbrs(lbr); 2033 intel_pmu_lbr_save_brstack(data, cpuc, event); 2034 } 2035 } 2036 2037 WARN_ONCE(next_record != __pebs + (format_size >> 48), 2038 "PEBS record size %llu, expected %llu, config %llx\n", 2039 format_size >> 48, 2040 (u64)(next_record - __pebs), 2041 basic->format_size); 2042 } 2043 2044 static inline void * get_next_pebs_record_by_bit(void * base,void * top,int bit)2045 get_next_pebs_record_by_bit(void *base, void *top, int bit) 2046 { 2047 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2048 void *at; 2049 u64 pebs_status; 2050 2051 /* 2052 * fmt0 does not have a status bitfield (does not use 2053 * perf_record_nhm format) 2054 */ 2055 if (x86_pmu.intel_cap.pebs_format < 1) 2056 return base; 2057 2058 if (base == NULL) 2059 return NULL; 2060 2061 for (at = base; at < top; at += cpuc->pebs_record_size) { 2062 unsigned long status = get_pebs_status(at); 2063 2064 if (test_bit(bit, (unsigned long *)&status)) { 2065 /* PEBS v3 has accurate status bits */ 2066 if (x86_pmu.intel_cap.pebs_format >= 3) 2067 return at; 2068 2069 if (status == (1 << bit)) 2070 return at; 2071 2072 /* clear non-PEBS bit and re-check */ 2073 pebs_status = status & cpuc->pebs_enabled; 2074 pebs_status &= PEBS_COUNTER_MASK; 2075 if (pebs_status == (1 << bit)) 2076 return at; 2077 } 2078 } 2079 return NULL; 2080 } 2081 intel_pmu_auto_reload_read(struct perf_event * event)2082 void intel_pmu_auto_reload_read(struct perf_event *event) 2083 { 2084 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)); 2085 2086 perf_pmu_disable(event->pmu); 2087 intel_pmu_drain_pebs_buffer(); 2088 perf_pmu_enable(event->pmu); 2089 } 2090 2091 /* 2092 * Special variant of intel_pmu_save_and_restart() for auto-reload. 2093 */ 2094 static int intel_pmu_save_and_restart_reload(struct perf_event * event,int count)2095 intel_pmu_save_and_restart_reload(struct perf_event *event, int count) 2096 { 2097 struct hw_perf_event *hwc = &event->hw; 2098 int shift = 64 - x86_pmu.cntval_bits; 2099 u64 period = hwc->sample_period; 2100 u64 prev_raw_count, new_raw_count; 2101 s64 new, old; 2102 2103 WARN_ON(!period); 2104 2105 /* 2106 * drain_pebs() only happens when the PMU is disabled. 2107 */ 2108 WARN_ON(this_cpu_read(cpu_hw_events.enabled)); 2109 2110 prev_raw_count = local64_read(&hwc->prev_count); 2111 rdpmcl(hwc->event_base_rdpmc, new_raw_count); 2112 local64_set(&hwc->prev_count, new_raw_count); 2113 2114 /* 2115 * Since the counter increments a negative counter value and 2116 * overflows on the sign switch, giving the interval: 2117 * 2118 * [-period, 0] 2119 * 2120 * the difference between two consecutive reads is: 2121 * 2122 * A) value2 - value1; 2123 * when no overflows have happened in between, 2124 * 2125 * B) (0 - value1) + (value2 - (-period)); 2126 * when one overflow happened in between, 2127 * 2128 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period)); 2129 * when @n overflows happened in between. 2130 * 2131 * Here A) is the obvious difference, B) is the extension to the 2132 * discrete interval, where the first term is to the top of the 2133 * interval and the second term is from the bottom of the next 2134 * interval and C) the extension to multiple intervals, where the 2135 * middle term is the whole intervals covered. 2136 * 2137 * An equivalent of C, by reduction, is: 2138 * 2139 * value2 - value1 + n * period 2140 */ 2141 new = ((s64)(new_raw_count << shift) >> shift); 2142 old = ((s64)(prev_raw_count << shift) >> shift); 2143 local64_add(new - old + count * period, &event->count); 2144 2145 local64_set(&hwc->period_left, -new); 2146 2147 perf_event_update_userpage(event); 2148 2149 return 0; 2150 } 2151 2152 static __always_inline void __intel_pmu_pebs_event(struct perf_event * event,struct pt_regs * iregs,struct perf_sample_data * data,void * base,void * top,int bit,int count,void (* setup_sample)(struct perf_event *,struct pt_regs *,void *,struct perf_sample_data *,struct pt_regs *))2153 __intel_pmu_pebs_event(struct perf_event *event, 2154 struct pt_regs *iregs, 2155 struct perf_sample_data *data, 2156 void *base, void *top, 2157 int bit, int count, 2158 void (*setup_sample)(struct perf_event *, 2159 struct pt_regs *, 2160 void *, 2161 struct perf_sample_data *, 2162 struct pt_regs *)) 2163 { 2164 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2165 struct hw_perf_event *hwc = &event->hw; 2166 struct x86_perf_regs perf_regs; 2167 struct pt_regs *regs = &perf_regs.regs; 2168 void *at = get_next_pebs_record_by_bit(base, top, bit); 2169 static struct pt_regs dummy_iregs; 2170 2171 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 2172 /* 2173 * Now, auto-reload is only enabled in fixed period mode. 2174 * The reload value is always hwc->sample_period. 2175 * May need to change it, if auto-reload is enabled in 2176 * freq mode later. 2177 */ 2178 intel_pmu_save_and_restart_reload(event, count); 2179 } else if (!intel_pmu_save_and_restart(event)) 2180 return; 2181 2182 if (!iregs) 2183 iregs = &dummy_iregs; 2184 2185 while (count > 1) { 2186 setup_sample(event, iregs, at, data, regs); 2187 perf_event_output(event, data, regs); 2188 at += cpuc->pebs_record_size; 2189 at = get_next_pebs_record_by_bit(at, top, bit); 2190 count--; 2191 } 2192 2193 setup_sample(event, iregs, at, data, regs); 2194 if (iregs == &dummy_iregs) { 2195 /* 2196 * The PEBS records may be drained in the non-overflow context, 2197 * e.g., large PEBS + context switch. Perf should treat the 2198 * last record the same as other PEBS records, and doesn't 2199 * invoke the generic overflow handler. 2200 */ 2201 perf_event_output(event, data, regs); 2202 } else { 2203 /* 2204 * All but the last records are processed. 2205 * The last one is left to be able to call the overflow handler. 2206 */ 2207 if (perf_event_overflow(event, data, regs)) 2208 x86_pmu_stop(event, 0); 2209 } 2210 } 2211 intel_pmu_drain_pebs_core(struct pt_regs * iregs,struct perf_sample_data * data)2212 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data) 2213 { 2214 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2215 struct debug_store *ds = cpuc->ds; 2216 struct perf_event *event = cpuc->events[0]; /* PMC0 only */ 2217 struct pebs_record_core *at, *top; 2218 int n; 2219 2220 if (!x86_pmu.pebs_active) 2221 return; 2222 2223 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; 2224 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; 2225 2226 /* 2227 * Whatever else happens, drain the thing 2228 */ 2229 ds->pebs_index = ds->pebs_buffer_base; 2230 2231 if (!test_bit(0, cpuc->active_mask)) 2232 return; 2233 2234 WARN_ON_ONCE(!event); 2235 2236 if (!event->attr.precise_ip) 2237 return; 2238 2239 n = top - at; 2240 if (n <= 0) { 2241 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2242 intel_pmu_save_and_restart_reload(event, 0); 2243 return; 2244 } 2245 2246 __intel_pmu_pebs_event(event, iregs, data, at, top, 0, n, 2247 setup_pebs_fixed_sample_data); 2248 } 2249 intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events * cpuc,int size)2250 static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size) 2251 { 2252 struct perf_event *event; 2253 int bit; 2254 2255 /* 2256 * The drain_pebs() could be called twice in a short period 2257 * for auto-reload event in pmu::read(). There are no 2258 * overflows have happened in between. 2259 * It needs to call intel_pmu_save_and_restart_reload() to 2260 * update the event->count for this case. 2261 */ 2262 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) { 2263 event = cpuc->events[bit]; 2264 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2265 intel_pmu_save_and_restart_reload(event, 0); 2266 } 2267 } 2268 intel_pmu_drain_pebs_nhm(struct pt_regs * iregs,struct perf_sample_data * data)2269 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data) 2270 { 2271 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2272 struct debug_store *ds = cpuc->ds; 2273 struct perf_event *event; 2274 void *base, *at, *top; 2275 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {}; 2276 short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {}; 2277 int max_pebs_events = intel_pmu_max_num_pebs(NULL); 2278 int bit, i, size; 2279 u64 mask; 2280 2281 if (!x86_pmu.pebs_active) 2282 return; 2283 2284 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; 2285 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; 2286 2287 ds->pebs_index = ds->pebs_buffer_base; 2288 2289 mask = x86_pmu.pebs_events_mask; 2290 size = max_pebs_events; 2291 if (x86_pmu.flags & PMU_FL_PEBS_ALL) { 2292 mask |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED; 2293 size = INTEL_PMC_IDX_FIXED + x86_pmu_max_num_counters_fixed(NULL); 2294 } 2295 2296 if (unlikely(base >= top)) { 2297 intel_pmu_pebs_event_update_no_drain(cpuc, size); 2298 return; 2299 } 2300 2301 for (at = base; at < top; at += x86_pmu.pebs_record_size) { 2302 struct pebs_record_nhm *p = at; 2303 u64 pebs_status; 2304 2305 pebs_status = p->status & cpuc->pebs_enabled; 2306 pebs_status &= mask; 2307 2308 /* PEBS v3 has more accurate status bits */ 2309 if (x86_pmu.intel_cap.pebs_format >= 3) { 2310 for_each_set_bit(bit, (unsigned long *)&pebs_status, size) 2311 counts[bit]++; 2312 2313 continue; 2314 } 2315 2316 /* 2317 * On some CPUs the PEBS status can be zero when PEBS is 2318 * racing with clearing of GLOBAL_STATUS. 2319 * 2320 * Normally we would drop that record, but in the 2321 * case when there is only a single active PEBS event 2322 * we can assume it's for that event. 2323 */ 2324 if (!pebs_status && cpuc->pebs_enabled && 2325 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) 2326 pebs_status = p->status = cpuc->pebs_enabled; 2327 2328 bit = find_first_bit((unsigned long *)&pebs_status, 2329 max_pebs_events); 2330 2331 if (!(x86_pmu.pebs_events_mask & (1 << bit))) 2332 continue; 2333 2334 /* 2335 * The PEBS hardware does not deal well with the situation 2336 * when events happen near to each other and multiple bits 2337 * are set. But it should happen rarely. 2338 * 2339 * If these events include one PEBS and multiple non-PEBS 2340 * events, it doesn't impact PEBS record. The record will 2341 * be handled normally. (slow path) 2342 * 2343 * If these events include two or more PEBS events, the 2344 * records for the events can be collapsed into a single 2345 * one, and it's not possible to reconstruct all events 2346 * that caused the PEBS record. It's called collision. 2347 * If collision happened, the record will be dropped. 2348 */ 2349 if (pebs_status != (1ULL << bit)) { 2350 for_each_set_bit(i, (unsigned long *)&pebs_status, size) 2351 error[i]++; 2352 continue; 2353 } 2354 2355 counts[bit]++; 2356 } 2357 2358 for_each_set_bit(bit, (unsigned long *)&mask, size) { 2359 if ((counts[bit] == 0) && (error[bit] == 0)) 2360 continue; 2361 2362 event = cpuc->events[bit]; 2363 if (WARN_ON_ONCE(!event)) 2364 continue; 2365 2366 if (WARN_ON_ONCE(!event->attr.precise_ip)) 2367 continue; 2368 2369 /* log dropped samples number */ 2370 if (error[bit]) { 2371 perf_log_lost_samples(event, error[bit]); 2372 2373 if (iregs && perf_event_account_interrupt(event)) 2374 x86_pmu_stop(event, 0); 2375 } 2376 2377 if (counts[bit]) { 2378 __intel_pmu_pebs_event(event, iregs, data, base, 2379 top, bit, counts[bit], 2380 setup_pebs_fixed_sample_data); 2381 } 2382 } 2383 } 2384 intel_pmu_drain_pebs_icl(struct pt_regs * iregs,struct perf_sample_data * data)2385 static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data) 2386 { 2387 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {}; 2388 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2389 struct debug_store *ds = cpuc->ds; 2390 struct perf_event *event; 2391 void *base, *at, *top; 2392 int bit; 2393 u64 mask; 2394 2395 if (!x86_pmu.pebs_active) 2396 return; 2397 2398 base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base; 2399 top = (struct pebs_basic *)(unsigned long)ds->pebs_index; 2400 2401 ds->pebs_index = ds->pebs_buffer_base; 2402 2403 mask = hybrid(cpuc->pmu, pebs_events_mask) | 2404 (hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED); 2405 2406 if (unlikely(base >= top)) { 2407 intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX); 2408 return; 2409 } 2410 2411 for (at = base; at < top; at += cpuc->pebs_record_size) { 2412 u64 pebs_status; 2413 2414 pebs_status = get_pebs_status(at) & cpuc->pebs_enabled; 2415 pebs_status &= mask; 2416 2417 for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) 2418 counts[bit]++; 2419 } 2420 2421 for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) { 2422 if (counts[bit] == 0) 2423 continue; 2424 2425 event = cpuc->events[bit]; 2426 if (WARN_ON_ONCE(!event)) 2427 continue; 2428 2429 if (WARN_ON_ONCE(!event->attr.precise_ip)) 2430 continue; 2431 2432 __intel_pmu_pebs_event(event, iregs, data, base, 2433 top, bit, counts[bit], 2434 setup_pebs_adaptive_sample_data); 2435 } 2436 } 2437 2438 /* 2439 * BTS, PEBS probe and setup 2440 */ 2441 intel_ds_init(void)2442 void __init intel_ds_init(void) 2443 { 2444 /* 2445 * No support for 32bit formats 2446 */ 2447 if (!boot_cpu_has(X86_FEATURE_DTES64)) 2448 return; 2449 2450 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); 2451 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); 2452 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; 2453 if (x86_pmu.version <= 4) 2454 x86_pmu.pebs_no_isolation = 1; 2455 2456 if (x86_pmu.pebs) { 2457 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; 2458 char *pebs_qual = ""; 2459 int format = x86_pmu.intel_cap.pebs_format; 2460 2461 if (format < 4) 2462 x86_pmu.intel_cap.pebs_baseline = 0; 2463 2464 switch (format) { 2465 case 0: 2466 pr_cont("PEBS fmt0%c, ", pebs_type); 2467 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); 2468 /* 2469 * Using >PAGE_SIZE buffers makes the WRMSR to 2470 * PERF_GLOBAL_CTRL in intel_pmu_enable_all() 2471 * mysteriously hang on Core2. 2472 * 2473 * As a workaround, we don't do this. 2474 */ 2475 x86_pmu.pebs_buffer_size = PAGE_SIZE; 2476 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; 2477 break; 2478 2479 case 1: 2480 pr_cont("PEBS fmt1%c, ", pebs_type); 2481 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); 2482 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 2483 break; 2484 2485 case 2: 2486 pr_cont("PEBS fmt2%c, ", pebs_type); 2487 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); 2488 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 2489 break; 2490 2491 case 3: 2492 pr_cont("PEBS fmt3%c, ", pebs_type); 2493 x86_pmu.pebs_record_size = 2494 sizeof(struct pebs_record_skl); 2495 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 2496 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; 2497 break; 2498 2499 case 5: 2500 x86_pmu.pebs_ept = 1; 2501 fallthrough; 2502 case 4: 2503 x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl; 2504 x86_pmu.pebs_record_size = sizeof(struct pebs_basic); 2505 if (x86_pmu.intel_cap.pebs_baseline) { 2506 x86_pmu.large_pebs_flags |= 2507 PERF_SAMPLE_BRANCH_STACK | 2508 PERF_SAMPLE_TIME; 2509 x86_pmu.flags |= PMU_FL_PEBS_ALL; 2510 x86_pmu.pebs_capable = ~0ULL; 2511 pebs_qual = "-baseline"; 2512 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS; 2513 } else { 2514 /* Only basic record supported */ 2515 x86_pmu.large_pebs_flags &= 2516 ~(PERF_SAMPLE_ADDR | 2517 PERF_SAMPLE_TIME | 2518 PERF_SAMPLE_DATA_SRC | 2519 PERF_SAMPLE_TRANSACTION | 2520 PERF_SAMPLE_REGS_USER | 2521 PERF_SAMPLE_REGS_INTR); 2522 } 2523 pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual); 2524 2525 if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) { 2526 pr_cont("PEBS-via-PT, "); 2527 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT; 2528 } 2529 2530 break; 2531 2532 default: 2533 pr_cont("no PEBS fmt%d%c, ", format, pebs_type); 2534 x86_pmu.pebs = 0; 2535 } 2536 } 2537 } 2538 perf_restore_debug_store(void)2539 void perf_restore_debug_store(void) 2540 { 2541 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2542 2543 if (!x86_pmu.bts && !x86_pmu.pebs) 2544 return; 2545 2546 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); 2547 } 2548