1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  S390 version
4  *    Copyright IBM Corp. 1999
5  *    Author(s): Hartmut Penner (hp@de.ibm.com),
6  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
7  *
8  *  Derived from "include/asm-i386/processor.h"
9  *    Copyright (C) 1994, Linus Torvalds
10  */
11 
12 #ifndef __ASM_S390_PROCESSOR_H
13 #define __ASM_S390_PROCESSOR_H
14 
15 #include <linux/bits.h>
16 
17 #define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
18 #define CIF_ENABLED_WAIT	5	/* in enabled wait state */
19 #define CIF_MCCK_GUEST		6	/* machine check happening in guest */
20 #define CIF_DEDICATED_CPU	7	/* this CPU is dedicated */
21 
22 #define _CIF_NOHZ_DELAY		BIT(CIF_NOHZ_DELAY)
23 #define _CIF_ENABLED_WAIT	BIT(CIF_ENABLED_WAIT)
24 #define _CIF_MCCK_GUEST		BIT(CIF_MCCK_GUEST)
25 #define _CIF_DEDICATED_CPU	BIT(CIF_DEDICATED_CPU)
26 
27 #define RESTART_FLAG_CTLREGS	_AC(1 << 0, U)
28 
29 #ifndef __ASSEMBLY__
30 
31 #include <linux/cpumask.h>
32 #include <linux/linkage.h>
33 #include <linux/irqflags.h>
34 #include <asm/fpu-types.h>
35 #include <asm/cpu.h>
36 #include <asm/page.h>
37 #include <asm/ptrace.h>
38 #include <asm/setup.h>
39 #include <asm/runtime_instr.h>
40 #include <asm/irqflags.h>
41 #include <asm/alternative.h>
42 
43 struct pcpu {
44 	unsigned long ec_mask;		/* bit mask for ec_xxx functions */
45 	unsigned long ec_clk;		/* sigp timestamp for ec_xxx */
46 	unsigned long flags;		/* per CPU flags */
47 	unsigned long capacity;		/* cpu capacity for scheduler */
48 	signed char state;		/* physical cpu state */
49 	signed char polarization;	/* physical polarization */
50 	u16 address;			/* physical cpu address */
51 };
52 
53 DECLARE_PER_CPU(struct pcpu, pcpu_devices);
54 
55 typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
56 
this_pcpu(void)57 static __always_inline struct pcpu *this_pcpu(void)
58 {
59 	return (struct pcpu *)(get_lowcore()->pcpu);
60 }
61 
set_cpu_flag(int flag)62 static __always_inline void set_cpu_flag(int flag)
63 {
64 	this_pcpu()->flags |= (1UL << flag);
65 }
66 
clear_cpu_flag(int flag)67 static __always_inline void clear_cpu_flag(int flag)
68 {
69 	this_pcpu()->flags &= ~(1UL << flag);
70 }
71 
test_cpu_flag(int flag)72 static __always_inline bool test_cpu_flag(int flag)
73 {
74 	return this_pcpu()->flags & (1UL << flag);
75 }
76 
test_and_set_cpu_flag(int flag)77 static __always_inline bool test_and_set_cpu_flag(int flag)
78 {
79 	if (test_cpu_flag(flag))
80 		return true;
81 	set_cpu_flag(flag);
82 	return false;
83 }
84 
test_and_clear_cpu_flag(int flag)85 static __always_inline bool test_and_clear_cpu_flag(int flag)
86 {
87 	if (!test_cpu_flag(flag))
88 		return false;
89 	clear_cpu_flag(flag);
90 	return true;
91 }
92 
93 /*
94  * Test CIF flag of another CPU. The caller needs to ensure that
95  * CPU hotplug can not happen, e.g. by disabling preemption.
96  */
test_cpu_flag_of(int flag,int cpu)97 static __always_inline bool test_cpu_flag_of(int flag, int cpu)
98 {
99 	return per_cpu(pcpu_devices, cpu).flags & (1UL << flag);
100 }
101 
102 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
103 
get_cpu_id(struct cpuid * ptr)104 static inline void get_cpu_id(struct cpuid *ptr)
105 {
106 	asm volatile("stidp %0" : "=Q" (*ptr));
107 }
108 
get_cpu_timer(void)109 static __always_inline unsigned long get_cpu_timer(void)
110 {
111 	unsigned long timer;
112 
113 	asm volatile("stpt	%[timer]" : [timer] "=Q" (timer));
114 	return timer;
115 }
116 
117 void s390_adjust_jiffies(void);
118 void s390_update_cpu_mhz(void);
119 void cpu_detect_mhz_feature(void);
120 
121 extern const struct seq_operations cpuinfo_op;
122 extern void execve_tail(void);
123 unsigned long vdso_text_size(void);
124 unsigned long vdso_size(void);
125 
126 /*
127  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
128  */
129 
130 #define TASK_SIZE		(test_thread_flag(TIF_31BIT) ? \
131 					_REGION3_SIZE : TASK_SIZE_MAX)
132 #define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
133 					(_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
134 #define TASK_SIZE_MAX		(-PAGE_SIZE)
135 
136 #define VDSO_BASE		(STACK_TOP + PAGE_SIZE)
137 #define VDSO_LIMIT		(test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
138 #define STACK_TOP		(VDSO_LIMIT - vdso_size() - PAGE_SIZE)
139 #define STACK_TOP_MAX		(_REGION2_SIZE - vdso_size() - PAGE_SIZE)
140 
141 #define HAVE_ARCH_PICK_MMAP_LAYOUT
142 
143 #define __stackleak_poison __stackleak_poison
__stackleak_poison(unsigned long erase_low,unsigned long erase_high,unsigned long poison)144 static __always_inline void __stackleak_poison(unsigned long erase_low,
145 					       unsigned long erase_high,
146 					       unsigned long poison)
147 {
148 	unsigned long tmp, count;
149 
150 	count = erase_high - erase_low;
151 	if (!count)
152 		return;
153 	asm volatile(
154 		"	cghi	%[count],8\n"
155 		"	je	2f\n"
156 		"	aghi	%[count],-(8+1)\n"
157 		"	srlg	%[tmp],%[count],8\n"
158 		"	ltgr	%[tmp],%[tmp]\n"
159 		"	jz	1f\n"
160 		"0:	stg	%[poison],0(%[addr])\n"
161 		"	mvc	8(256-8,%[addr]),0(%[addr])\n"
162 		"	la	%[addr],256(%[addr])\n"
163 		"	brctg	%[tmp],0b\n"
164 		"1:	stg	%[poison],0(%[addr])\n"
165 		"	larl	%[tmp],3f\n"
166 		"	ex	%[count],0(%[tmp])\n"
167 		"	j	4f\n"
168 		"2:	stg	%[poison],0(%[addr])\n"
169 		"	j	4f\n"
170 		"3:	mvc	8(1,%[addr]),0(%[addr])\n"
171 		"4:\n"
172 		: [addr] "+&a" (erase_low), [count] "+&d" (count), [tmp] "=&a" (tmp)
173 		: [poison] "d" (poison)
174 		: "memory", "cc"
175 		);
176 }
177 
178 /*
179  * Thread structure
180  */
181 struct thread_struct {
182 	unsigned int  acrs[NUM_ACRS];
183 	unsigned long ksp;			/* kernel stack pointer */
184 	unsigned long user_timer;		/* task cputime in user space */
185 	unsigned long guest_timer;		/* task cputime in kvm guest */
186 	unsigned long system_timer;		/* task cputime in kernel space */
187 	unsigned long hardirq_timer;		/* task cputime in hardirq context */
188 	unsigned long softirq_timer;		/* task cputime in softirq context */
189 	const sys_call_ptr_t *sys_call_table;	/* system call table address */
190 	unsigned long gmap_addr;		/* address of last gmap fault. */
191 	unsigned int gmap_write_flag;		/* gmap fault write indication */
192 	unsigned int gmap_int_code;		/* int code of last gmap fault */
193 	unsigned int gmap_pfault;		/* signal of a pending guest pfault */
194 	int ufpu_flags;				/* user fpu flags */
195 	int kfpu_flags;				/* kernel fpu flags */
196 
197 	/* Per-thread information related to debugging */
198 	struct per_regs per_user;		/* User specified PER registers */
199 	struct per_event per_event;		/* Cause of the last PER trap */
200 	unsigned long per_flags;		/* Flags to control debug behavior */
201 	unsigned int system_call;		/* system call number in signal */
202 	unsigned long last_break;		/* last breaking-event-address. */
203 	/* pfault_wait is used to block the process on a pfault event */
204 	unsigned long pfault_wait;
205 	struct list_head list;
206 	/* cpu runtime instrumentation */
207 	struct runtime_instr_cb *ri_cb;
208 	struct gs_cb *gs_cb;			/* Current guarded storage cb */
209 	struct gs_cb *gs_bc_cb;			/* Broadcast guarded storage cb */
210 	struct pgm_tdb trap_tdb;		/* Transaction abort diagnose block */
211 	struct fpu ufpu;			/* User FP and VX register save area */
212 	struct fpu kfpu;			/* Kernel FP and VX register save area */
213 };
214 
215 /* Flag to disable transactions. */
216 #define PER_FLAG_NO_TE			1UL
217 /* Flag to enable random transaction aborts. */
218 #define PER_FLAG_TE_ABORT_RAND		2UL
219 /* Flag to specify random transaction abort mode:
220  * - abort each transaction at a random instruction before TEND if set.
221  * - abort random transactions at a random instruction if cleared.
222  */
223 #define PER_FLAG_TE_ABORT_RAND_TEND	4UL
224 
225 typedef struct thread_struct thread_struct;
226 
227 #define ARCH_MIN_TASKALIGN	8
228 
229 #define INIT_THREAD {							\
230 	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
231 	.last_break = 1,						\
232 }
233 
234 /*
235  * Do necessary setup to start up a new thread.
236  */
237 #define start_thread(regs, new_psw, new_stackp) do {			\
238 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
239 	regs->psw.addr	= new_psw;					\
240 	regs->gprs[15]	= new_stackp;					\
241 	execve_tail();							\
242 } while (0)
243 
244 #define start_thread31(regs, new_psw, new_stackp) do {			\
245 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
246 	regs->psw.addr	= new_psw;					\
247 	regs->gprs[15]	= new_stackp;					\
248 	execve_tail();							\
249 } while (0)
250 
251 struct task_struct;
252 struct mm_struct;
253 struct seq_file;
254 struct pt_regs;
255 
256 void show_registers(struct pt_regs *regs);
257 void show_cacheinfo(struct seq_file *m);
258 
259 /* Free guarded storage control block */
260 void guarded_storage_release(struct task_struct *tsk);
261 void gs_load_bc_cb(struct pt_regs *regs);
262 
263 unsigned long __get_wchan(struct task_struct *p);
264 #define task_pt_regs(tsk) ((struct pt_regs *) \
265         (task_stack_page(tsk) + THREAD_SIZE) - 1)
266 #define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
267 #define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])
268 
269 /* Has task runtime instrumentation enabled ? */
270 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
271 
272 /* avoid using global register due to gcc bug in versions < 8.4 */
273 #define current_stack_pointer (__current_stack_pointer())
274 
__current_stack_pointer(void)275 static __always_inline unsigned long __current_stack_pointer(void)
276 {
277 	unsigned long sp;
278 
279 	asm volatile("lgr %0,15" : "=d" (sp));
280 	return sp;
281 }
282 
on_thread_stack(void)283 static __always_inline bool on_thread_stack(void)
284 {
285 	unsigned long ksp = get_lowcore()->kernel_stack;
286 
287 	return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
288 }
289 
stap(void)290 static __always_inline unsigned short stap(void)
291 {
292 	unsigned short cpu_address;
293 
294 	asm volatile("stap %0" : "=Q" (cpu_address));
295 	return cpu_address;
296 }
297 
298 #define cpu_relax() barrier()
299 
300 #define ECAG_CACHE_ATTRIBUTE	0
301 #define ECAG_CPU_ATTRIBUTE	1
302 
__ecag(unsigned int asi,unsigned char parm)303 static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
304 {
305 	unsigned long val;
306 
307 	asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
308 	return val;
309 }
310 
psw_set_key(unsigned int key)311 static inline void psw_set_key(unsigned int key)
312 {
313 	asm volatile("spka 0(%0)" : : "d" (key));
314 }
315 
316 /*
317  * Set PSW to specified value.
318  */
__load_psw(psw_t psw)319 static inline void __load_psw(psw_t psw)
320 {
321 	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
322 }
323 
324 /*
325  * Set PSW mask to specified value, while leaving the
326  * PSW addr pointing to the next instruction.
327  */
__load_psw_mask(unsigned long mask)328 static __always_inline void __load_psw_mask(unsigned long mask)
329 {
330 	psw_t psw __uninitialized;
331 	unsigned long addr;
332 
333 	psw.mask = mask;
334 
335 	asm volatile(
336 		"	larl	%0,1f\n"
337 		"	stg	%0,%1\n"
338 		"	lpswe	%2\n"
339 		"1:"
340 		: "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
341 }
342 
343 /*
344  * Extract current PSW mask
345  */
__extract_psw(void)346 static inline unsigned long __extract_psw(void)
347 {
348 	unsigned int reg1, reg2;
349 
350 	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
351 	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
352 }
353 
__local_mcck_save(void)354 static inline unsigned long __local_mcck_save(void)
355 {
356 	unsigned long mask = __extract_psw();
357 
358 	__load_psw_mask(mask & ~PSW_MASK_MCHECK);
359 	return mask & PSW_MASK_MCHECK;
360 }
361 
362 #define local_mcck_save(mflags)			\
363 do {						\
364 	typecheck(unsigned long, mflags);	\
365 	mflags = __local_mcck_save();		\
366 } while (0)
367 
local_mcck_restore(unsigned long mflags)368 static inline void local_mcck_restore(unsigned long mflags)
369 {
370 	unsigned long mask = __extract_psw();
371 
372 	mask &= ~PSW_MASK_MCHECK;
373 	__load_psw_mask(mask | mflags);
374 }
375 
local_mcck_disable(void)376 static inline void local_mcck_disable(void)
377 {
378 	__local_mcck_save();
379 }
380 
local_mcck_enable(void)381 static inline void local_mcck_enable(void)
382 {
383 	__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
384 }
385 
386 /*
387  * Rewind PSW instruction address by specified number of bytes.
388  */
__rewind_psw(psw_t psw,unsigned long ilc)389 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
390 {
391 	unsigned long mask;
392 
393 	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
394 	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
395 					  (1UL << 24) - 1;
396 	return (psw.addr - ilc) & mask;
397 }
398 
399 /*
400  * Function to drop a processor into disabled wait state
401  */
disabled_wait(void)402 static __always_inline void __noreturn disabled_wait(void)
403 {
404 	psw_t psw;
405 
406 	psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
407 	psw.addr = _THIS_IP_;
408 	__load_psw(psw);
409 	while (1);
410 }
411 
412 #define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL
413 
regs_irqs_disabled(struct pt_regs * regs)414 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
415 {
416 	return arch_irqs_disabled_flags(regs->psw.mask);
417 }
418 
bpon(void)419 static __always_inline void bpon(void)
420 {
421 	asm volatile(ALTERNATIVE("nop", ".insn	rrf,0xb2e80000,0,0,13,0", ALT_SPEC(82)));
422 }
423 
424 #endif /* __ASSEMBLY__ */
425 
426 #endif /* __ASM_S390_PROCESSOR_H */
427