1  /* SPDX-License-Identifier: GPL-2.0-or-later */
2  /*
3   * Copyright 2009 Freescale Semiconductor, Inc.
4   *
5   * provides masks and opcode images for use by code generation, emulation
6   * and for instructions that older assemblers might not know about
7   */
8  #ifndef _ASM_POWERPC_PPC_OPCODE_H
9  #define _ASM_POWERPC_PPC_OPCODE_H
10  
11  #include <asm/asm-const.h>
12  
13  #define	__REG_R0	0
14  #define	__REG_R1	1
15  #define	__REG_R2	2
16  #define	__REG_R3	3
17  #define	__REG_R4	4
18  #define	__REG_R5	5
19  #define	__REG_R6	6
20  #define	__REG_R7	7
21  #define	__REG_R8	8
22  #define	__REG_R9	9
23  #define	__REG_R10	10
24  #define	__REG_R11	11
25  #define	__REG_R12	12
26  #define	__REG_R13	13
27  #define	__REG_R14	14
28  #define	__REG_R15	15
29  #define	__REG_R16	16
30  #define	__REG_R17	17
31  #define	__REG_R18	18
32  #define	__REG_R19	19
33  #define	__REG_R20	20
34  #define	__REG_R21	21
35  #define	__REG_R22	22
36  #define	__REG_R23	23
37  #define	__REG_R24	24
38  #define	__REG_R25	25
39  #define	__REG_R26	26
40  #define	__REG_R27	27
41  #define	__REG_R28	28
42  #define	__REG_R29	29
43  #define	__REG_R30	30
44  #define	__REG_R31	31
45  
46  #define	__REGA0_0	0
47  #define	__REGA0_R1	1
48  #define	__REGA0_R2	2
49  #define	__REGA0_R3	3
50  #define	__REGA0_R4	4
51  #define	__REGA0_R5	5
52  #define	__REGA0_R6	6
53  #define	__REGA0_R7	7
54  #define	__REGA0_R8	8
55  #define	__REGA0_R9	9
56  #define	__REGA0_R10	10
57  #define	__REGA0_R11	11
58  #define	__REGA0_R12	12
59  #define	__REGA0_R13	13
60  #define	__REGA0_R14	14
61  #define	__REGA0_R15	15
62  #define	__REGA0_R16	16
63  #define	__REGA0_R17	17
64  #define	__REGA0_R18	18
65  #define	__REGA0_R19	19
66  #define	__REGA0_R20	20
67  #define	__REGA0_R21	21
68  #define	__REGA0_R22	22
69  #define	__REGA0_R23	23
70  #define	__REGA0_R24	24
71  #define	__REGA0_R25	25
72  #define	__REGA0_R26	26
73  #define	__REGA0_R27	27
74  #define	__REGA0_R28	28
75  #define	__REGA0_R29	29
76  #define	__REGA0_R30	30
77  #define	__REGA0_R31	31
78  
79  /* For use with PPC_RAW_() macros */
80  #define	_R0	0
81  #define	_R1	1
82  #define	_R2	2
83  #define	_R3	3
84  #define	_R4	4
85  #define	_R5	5
86  #define	_R6	6
87  #define	_R7	7
88  #define	_R8	8
89  #define	_R9	9
90  #define	_R10	10
91  #define	_R11	11
92  #define	_R12	12
93  #define	_R13	13
94  #define	_R14	14
95  #define	_R15	15
96  #define	_R16	16
97  #define	_R17	17
98  #define	_R18	18
99  #define	_R19	19
100  #define	_R20	20
101  #define	_R21	21
102  #define	_R22	22
103  #define	_R23	23
104  #define	_R24	24
105  #define	_R25	25
106  #define	_R26	26
107  #define	_R27	27
108  #define	_R28	28
109  #define	_R29	29
110  #define	_R30	30
111  #define	_R31	31
112  
113  #define IMM_L(i)               ((uintptr_t)(i) & 0xffff)
114  #define IMM_DS(i)              ((uintptr_t)(i) & 0xfffc)
115  #define IMM_DQ(i)              ((uintptr_t)(i) & 0xfff0)
116  #define IMM_D0(i)              (((uintptr_t)(i) >> 16) & 0x3ffff)
117  #define IMM_D1(i)              IMM_L(i)
118  
119  /*
120   * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
121   * (e.g. LD, ADDI).  If the bottom 16 bits is "-ve", add another bit into the
122   * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
123   *
124   * XXX: should these mask out possible sign bits?
125   */
126  #define IMM_H(i)                ((uintptr_t)(i)>>16)
127  #define IMM_HA(i)               (((uintptr_t)(i)>>16) +                       \
128  					(((uintptr_t)(i) & 0x8000) >> 15))
129  
130  /*
131   * 18-bit immediate helper for prefix 18-bit upper immediate si0 field.
132   */
133  #define IMM_H18(i)              (((uintptr_t)(i)>>16) & 0x3ffff)
134  
135  
136  /* opcode and xopcode for instructions */
137  #define OP_PREFIX	1
138  #define OP_TRAP_64	2
139  #define OP_TRAP		3
140  #define OP_SC		17
141  #define OP_19		19
142  #define OP_31		31
143  #define OP_LWZ		32
144  #define OP_LWZU		33
145  #define OP_LBZ		34
146  #define OP_LBZU		35
147  #define OP_STW		36
148  #define OP_STWU		37
149  #define OP_STB		38
150  #define OP_STBU		39
151  #define OP_LHZ		40
152  #define OP_LHZU		41
153  #define OP_LHA		42
154  #define OP_LHAU		43
155  #define OP_STH		44
156  #define OP_STHU		45
157  #define OP_LMW		46
158  #define OP_STMW		47
159  #define OP_LFS		48
160  #define OP_LFSU		49
161  #define OP_LFD		50
162  #define OP_LFDU		51
163  #define OP_STFS		52
164  #define OP_STFSU	53
165  #define OP_STFD		54
166  #define OP_STFDU	55
167  #define OP_LQ		56
168  #define OP_LD		58
169  #define OP_STD		62
170  
171  #define OP_19_XOP_RFID		18
172  #define OP_19_XOP_RFMCI		38
173  #define OP_19_XOP_RFDI		39
174  #define OP_19_XOP_RFI		50
175  #define OP_19_XOP_RFCI		51
176  #define OP_19_XOP_RFSCV		82
177  #define OP_19_XOP_HRFID		274
178  #define OP_19_XOP_URFID		306
179  #define OP_19_XOP_STOP		370
180  #define OP_19_XOP_DOZE		402
181  #define OP_19_XOP_NAP		434
182  #define OP_19_XOP_SLEEP		466
183  #define OP_19_XOP_RVWINKLE	498
184  
185  #define OP_31_XOP_TRAP      4
186  #define OP_31_XOP_LDX       21
187  #define OP_31_XOP_LWZX      23
188  #define OP_31_XOP_LDUX      53
189  #define OP_31_XOP_DCBST     54
190  #define OP_31_XOP_LWZUX     55
191  #define OP_31_XOP_TRAP_64   68
192  #define OP_31_XOP_DCBF      86
193  #define OP_31_XOP_LBZX      87
194  #define OP_31_XOP_STDX      149
195  #define OP_31_XOP_STWX      151
196  #define OP_31_XOP_STDUX     181
197  #define OP_31_XOP_STWUX     183
198  #define OP_31_XOP_STBX      215
199  #define OP_31_XOP_LBZUX     119
200  #define OP_31_XOP_STBUX     247
201  #define OP_31_XOP_LHZX      279
202  #define OP_31_XOP_LHZUX     311
203  #define OP_31_XOP_MSGSNDP   142
204  #define OP_31_XOP_MSGCLRP   174
205  #define OP_31_XOP_MTMSR     146
206  #define OP_31_XOP_MTMSRD    178
207  #define OP_31_XOP_TLBIE     306
208  #define OP_31_XOP_MFSPR     339
209  #define OP_31_XOP_LWAX      341
210  #define OP_31_XOP_LHAX      343
211  #define OP_31_XOP_LWAUX     373
212  #define OP_31_XOP_LHAUX     375
213  #define OP_31_XOP_STHX      407
214  #define OP_31_XOP_STHUX     439
215  #define OP_31_XOP_MTSPR     467
216  #define OP_31_XOP_DCBI      470
217  #define OP_31_XOP_LDBRX     532
218  #define OP_31_XOP_LWBRX     534
219  #define OP_31_XOP_TLBSYNC   566
220  #define OP_31_XOP_STDBRX    660
221  #define OP_31_XOP_STWBRX    662
222  #define OP_31_XOP_STFSX	    663
223  #define OP_31_XOP_STFSUX    695
224  #define OP_31_XOP_STFDX     727
225  #define OP_31_XOP_HASHCHK   754
226  #define OP_31_XOP_STFDUX    759
227  #define OP_31_XOP_LHBRX     790
228  #define OP_31_XOP_LFIWAX    855
229  #define OP_31_XOP_LFIWZX    887
230  #define OP_31_XOP_STHBRX    918
231  #define OP_31_XOP_STFIWX    983
232  
233  /* VSX Scalar Load Instructions */
234  #define OP_31_XOP_LXSDX         588
235  #define OP_31_XOP_LXSSPX        524
236  #define OP_31_XOP_LXSIWAX       76
237  #define OP_31_XOP_LXSIWZX       12
238  
239  /* VSX Scalar Store Instructions */
240  #define OP_31_XOP_STXSDX        716
241  #define OP_31_XOP_STXSSPX       652
242  #define OP_31_XOP_STXSIWX       140
243  
244  /* VSX Vector Load Instructions */
245  #define OP_31_XOP_LXVD2X        844
246  #define OP_31_XOP_LXVW4X        780
247  
248  /* VSX Vector Load and Splat Instruction */
249  #define OP_31_XOP_LXVDSX        332
250  
251  /* VSX Vector Store Instructions */
252  #define OP_31_XOP_STXVD2X       972
253  #define OP_31_XOP_STXVW4X       908
254  
255  #define OP_31_XOP_LFSX          535
256  #define OP_31_XOP_LFSUX         567
257  #define OP_31_XOP_LFDX          599
258  #define OP_31_XOP_LFDUX		631
259  
260  /* VMX Vector Load Instructions */
261  #define OP_31_XOP_LVX           103
262  
263  /* VMX Vector Store Instructions */
264  #define OP_31_XOP_STVX          231
265  
266  /* sorted alphabetically */
267  #define PPC_INST_BCCTR_FLUSH		0x4c400420
268  #define PPC_INST_COPY			0x7c20060c
269  #define PPC_INST_DCBA			0x7c0005ec
270  #define PPC_INST_DCBA_MASK		0xfc0007fe
271  #define PPC_INST_DSSALL			0x7e00066c
272  #define PPC_INST_ISEL			0x7c00001e
273  #define PPC_INST_ISEL_MASK		0xfc00003e
274  #define PPC_INST_LSWI			0x7c0004aa
275  #define PPC_INST_LSWX			0x7c00042a
276  #define PPC_INST_LWSYNC			0x7c2004ac
277  #define PPC_INST_SYNC			0x7c0004ac
278  #define PPC_INST_SYNC_MASK		0xfc0007fe
279  #define PPC_INST_MCRXR			0x7c000400
280  #define PPC_INST_MCRXR_MASK		0xfc0007fe
281  #define PPC_INST_MFSPR_PVR		0x7c1f42a6
282  #define PPC_INST_MFSPR_PVR_MASK		0xfc1ffffe
283  #define PPC_INST_MTMSRD			0x7c000164
284  #define PPC_INST_PASTE			0x7c20070d
285  #define PPC_INST_PASTE_MASK		0xfc2007ff
286  #define PPC_INST_POPCNTB		0x7c0000f4
287  #define PPC_INST_POPCNTB_MASK		0xfc0007fe
288  #define PPC_INST_RFEBB			0x4c000124
289  #define PPC_INST_RFID			0x4c000024
290  #define PPC_INST_MFSPR_DSCR		0x7c1102a6
291  #define PPC_INST_MFSPR_DSCR_MASK	0xfc1ffffe
292  #define PPC_INST_MTSPR_DSCR		0x7c1103a6
293  #define PPC_INST_MTSPR_DSCR_MASK	0xfc1ffffe
294  #define PPC_INST_MFSPR_DSCR_USER	0x7c0302a6
295  #define PPC_INST_MFSPR_DSCR_USER_MASK	0xfc1ffffe
296  #define PPC_INST_MTSPR_DSCR_USER	0x7c0303a6
297  #define PPC_INST_MTSPR_DSCR_USER_MASK	0xfc1ffffe
298  #define PPC_INST_STRING			0x7c00042a
299  #define PPC_INST_STRING_MASK		0xfc0007fe
300  #define PPC_INST_STRING_GEN_MASK	0xfc00067e
301  #define PPC_INST_STSWI			0x7c0005aa
302  #define PPC_INST_STSWX			0x7c00052a
303  #define PPC_INST_TRECHKPT		0x7c0007dd
304  #define PPC_INST_TRECLAIM		0x7c00075d
305  #define PPC_INST_TSR			0x7c0005dd
306  #define PPC_INST_BRANCH_COND		0x40800000
307  
308  /* Prefixes */
309  #define PPC_INST_LFS			0xc0000000
310  #define PPC_INST_STFS			0xd0000000
311  #define PPC_INST_LFD			0xc8000000
312  #define PPC_INST_STFD			0xd8000000
313  #define PPC_PREFIX_MLS			0x06000000
314  #define PPC_PREFIX_8LS			0x04000000
315  
316  /* Prefixed instructions */
317  #define PPC_INST_PADDI			0x38000000
318  #define PPC_INST_PLD			0xe4000000
319  #define PPC_INST_PSTD			0xf4000000
320  
321  /* macros to insert fields into opcodes */
322  #define ___PPC_RA(a)	(((a) & 0x1f) << 16)
323  #define ___PPC_RB(b)	(((b) & 0x1f) << 11)
324  #define ___PPC_RC(c)	(((c) & 0x1f) << 6)
325  #define ___PPC_RS(s)	(((s) & 0x1f) << 21)
326  #define ___PPC_RT(t)	___PPC_RS(t)
327  #define ___PPC_R(r)	(((r) & 0x1) << 16)
328  #define ___PPC_PRS(prs)	(((prs) & 0x1) << 17)
329  #define ___PPC_RIC(ric)	(((ric) & 0x3) << 18)
330  #define __PPC_RA(a)	___PPC_RA(__REG_##a)
331  #define __PPC_RA0(a)	___PPC_RA(__REGA0_##a)
332  #define __PPC_RB(b)	___PPC_RB(__REG_##b)
333  #define __PPC_RS(s)	___PPC_RS(__REG_##s)
334  #define __PPC_RT(t)	___PPC_RT(__REG_##t)
335  #define __PPC_XA(a)	((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
336  #define __PPC_XB(b)	((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
337  #define __PPC_XS(s)	((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
338  #define __PPC_XT(s)	__PPC_XS(s)
339  #define __PPC_XSP(s)	((((s) & 0x1e) | (((s) >> 5) & 0x1)) << 21)
340  #define __PPC_XTP(s)	__PPC_XSP(s)
341  #define __PPC_T_TLB(t)	(((t) & 0x3) << 21)
342  #define __PPC_PL(p)	(((p) & 0x3) << 16)
343  #define __PPC_WC(w)	(((w) & 0x3) << 21)
344  #define __PPC_WS(w)	(((w) & 0x1f) << 11)
345  #define __PPC_SH(s)	__PPC_WS(s)
346  #define __PPC_SH64(s)	(__PPC_SH(s) | (((s) & 0x20) >> 4))
347  #define __PPC_MB(s)	___PPC_RC(s)
348  #define __PPC_ME(s)	(((s) & 0x1f) << 1)
349  #define __PPC_MB64(s)	(__PPC_MB(s) | ((s) & 0x20))
350  #define __PPC_ME64(s)	__PPC_MB64(s)
351  #define __PPC_BI(s)	(((s) & 0x1f) << 16)
352  #define __PPC_CT(t)	(((t) & 0x0f) << 21)
353  #define __PPC_SPR(r)	((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
354  #define __PPC_RC21	(0x1 << 10)
355  #define __PPC_PRFX_R(r)	(((r) & 0x1) << 20)
356  #define __PPC_EH(eh)	(((eh) & 0x1) << 0)
357  
358  /*
359   * Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
360   * has high bit set, high 16 bits must be adjusted. These macros do that (stolen
361   * from binutils).
362   */
363  #define PPC_LO(v)	((v) & 0xffff)
364  #define PPC_HI(v)	(((v) >> 16) & 0xffff)
365  #define PPC_HA(v)	PPC_HI((v) + 0x8000)
366  #define PPC_HIGHER(v)	(((v) >> 32) & 0xffff)
367  #define PPC_HIGHEST(v)	(((v) >> 48) & 0xffff)
368  
369  /* LI Field */
370  #define PPC_LI_MASK	0x03fffffc
371  #define PPC_LI(v)	((v) & PPC_LI_MASK)
372  
373  /* Base instruction encoding */
374  #define PPC_RAW_CP_ABORT		(0x7c00068c)
375  #define PPC_RAW_COPY(a, b)		(PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b))
376  #define PPC_RAW_DARN(t, l)		(0x7c0005e6 | ___PPC_RT(t) | (((l) & 0x3) << 16))
377  #define PPC_RAW_DCBAL(a, b)		(0x7c2005ec | __PPC_RA(a) | __PPC_RB(b))
378  #define PPC_RAW_DCBZL(a, b)		(0x7c2007ec | __PPC_RA(a) | __PPC_RB(b))
379  #define PPC_RAW_LQARX(t, a, b, eh)	(0x7c000228 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
380  #define PPC_RAW_LDARX(t, a, b, eh)	(0x7c0000a8 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
381  #define PPC_RAW_LWARX(t, a, b, eh)	(0x7c000028 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
382  #define PPC_RAW_PHWSYNC			(0x7c8004ac)
383  #define PPC_RAW_PLWSYNC			(0x7ca004ac)
384  #define PPC_RAW_STQCX(t, a, b)		(0x7c00016d | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
385  #define PPC_RAW_MADDHD(t, a, b, c)	(0x10000030 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
386  #define PPC_RAW_MADDHDU(t, a, b, c)	(0x10000031 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
387  #define PPC_RAW_MADDLD(t, a, b, c)	(0x10000033 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
388  #define PPC_RAW_MSGSND(b)		(0x7c00019c | ___PPC_RB(b))
389  #define PPC_RAW_MSGSYNC			(0x7c0006ec)
390  #define PPC_RAW_MSGCLR(b)		(0x7c0001dc | ___PPC_RB(b))
391  #define PPC_RAW_MSGSNDP(b)		(0x7c00011c | ___PPC_RB(b))
392  #define PPC_RAW_MSGCLRP(b)		(0x7c00015c | ___PPC_RB(b))
393  #define PPC_RAW_PASTE(a, b)		(0x7c20070d | ___PPC_RA(a) | ___PPC_RB(b))
394  #define PPC_RAW_POPCNTB(a, s)		(PPC_INST_POPCNTB | __PPC_RA(a) | __PPC_RS(s))
395  #define PPC_RAW_POPCNTD(a, s)		(0x7c0003f4 | __PPC_RA(a) | __PPC_RS(s))
396  #define PPC_RAW_POPCNTW(a, s)		(0x7c0002f4 | __PPC_RA(a) | __PPC_RS(s))
397  #define PPC_RAW_RFCI			(0x4c000066)
398  #define PPC_RAW_RFDI			(0x4c00004e)
399  #define PPC_RAW_RFMCI			(0x4c00004c)
400  #define PPC_RAW_TLBILX_LPID		(0x7c000024)
401  #define PPC_RAW_TLBILX(t, a, b)		(0x7c000024 | __PPC_T_TLB(t) | 	__PPC_RA0(a) | __PPC_RB(b))
402  #define PPC_RAW_WAIT_v203		(0x7c00007c)
403  #define PPC_RAW_WAIT(w, p)		(0x7c00003c | __PPC_WC(w) | __PPC_PL(p))
404  #define PPC_RAW_TLBIE(lp, a)		(0x7c000264 | ___PPC_RB(a) | ___PPC_RS(lp))
405  #define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \
406  	(0x7c000264 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
407  #define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \
408  	(0x7c000224 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
409  #define PPC_RAW_TLBIEL_v205(rb, l)	(0x7c000224 | ___PPC_RB(rb) | (l << 21))
410  #define PPC_RAW_TLBSRX_DOT(a, b)	(0x7c0006a5 | __PPC_RA0(a) | __PPC_RB(b))
411  #define PPC_RAW_TLBIVAX(a, b)		(0x7c000624 | __PPC_RA0(a) | __PPC_RB(b))
412  #define PPC_RAW_ERATWE(s, a, w)		(0x7c0001a6 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
413  #define PPC_RAW_ERATRE(s, a, w)		(0x7c000166 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
414  #define PPC_RAW_ERATILX(t, a, b)	(0x7c000066 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
415  #define PPC_RAW_ERATIVAX(s, a, b)	(0x7c000666 | __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
416  #define PPC_RAW_ERATSX(t, a, w)		(0x7c000126 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
417  #define PPC_RAW_ERATSX_DOT(t, a, w)	(0x7c000127 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
418  #define PPC_RAW_SLBFEE_DOT(t, b)	(0x7c0007a7 | __PPC_RT(t) | __PPC_RB(b))
419  #define __PPC_RAW_SLBFEE_DOT(t, b)	(0x7c0007a7 | ___PPC_RT(t) | ___PPC_RB(b))
420  #define PPC_RAW_ICBT(c, a, b)		(0x7c00002c | __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
421  #define PPC_RAW_LBZCIX(t, a, b)		(0x7c0006aa | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
422  #define PPC_RAW_STBCIX(s, a, b)		(0x7c0007aa | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
423  #define PPC_RAW_DCBFPS(a, b)		(0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
424  #define PPC_RAW_DCBSTPS(a, b)		(0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
425  #define PPC_RAW_SC()			(0x44000002)
426  #define PPC_RAW_SYNC()			(0x7c0004ac)
427  #define PPC_RAW_ISYNC()			(0x4c00012c)
428  
429  /*
430   * Define what the VSX XX1 form instructions will look like, then add
431   * the 128 bit load store instructions based on that.
432   */
433  #define VSX_XX1(s, a, b)		(__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
434  #define VSX_XX3(t, a, b)		(__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
435  #define PPC_RAW_STXVD2X(s, a, b)	(0x7c000798 | VSX_XX1((s), a, b))
436  #define PPC_RAW_LXVD2X(s, a, b)		(0x7c000698 | VSX_XX1((s), a, b))
437  #define PPC_RAW_MFVRD(a, t)		(0x7c000066 | VSX_XX1((t) + 32, a, R0))
438  #define PPC_RAW_MTVRD(t, a)		(0x7c000166 | VSX_XX1((t) + 32, a, R0))
439  #define PPC_RAW_VPMSUMW(t, a, b)	(0x10000488 | VSX_XX3((t), a, b))
440  #define PPC_RAW_VPMSUMD(t, a, b)	(0x100004c8 | VSX_XX3((t), a, b))
441  #define PPC_RAW_XXLOR(t, a, b)		(0xf0000490 | VSX_XX3((t), a, b))
442  #define PPC_RAW_XXSWAPD(t, a)		(0xf0000250 | VSX_XX3((t), a, a))
443  #define PPC_RAW_XVCPSGNDP(t, a, b)	((0xf0000780 | VSX_XX3((t), (a), (b))))
444  #define PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc) \
445  	((0x1000002d | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
446  #define PPC_RAW_LXVP(xtp, a, i)		(0x18000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_DQ(i))
447  #define PPC_RAW_STXVP(xsp, a, i)	(0x18000001 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_DQ(i))
448  #define PPC_RAW_LXVPX(xtp, a, b)	(0x7c00029a | __PPC_XTP(xtp) | ___PPC_RA(a) | ___PPC_RB(b))
449  #define PPC_RAW_STXVPX(xsp, a, b)	(0x7c00039a | __PPC_XSP(xsp) | ___PPC_RA(a) | ___PPC_RB(b))
450  #define PPC_RAW_PLXVP_P(xtp, i, a, pr)	(PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i))
451  #define PPC_RAW_PLXVP_S(xtp, i, a, pr)	(0xe8000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_D1(i))
452  #define PPC_RAW_PSTXVP_P(xsp, i, a, pr)	(PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i))
453  #define PPC_RAW_PSTXVP_S(xsp, i, a, pr)	(0xf8000000 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_D1(i))
454  #define PPC_RAW_NAP			(0x4c000364)
455  #define PPC_RAW_SLEEP			(0x4c0003a4)
456  #define PPC_RAW_WINKLE			(0x4c0003e4)
457  #define PPC_RAW_STOP			(0x4c0002e4)
458  #define PPC_RAW_CLRBHRB			(0x7c00035c)
459  #define PPC_RAW_MFBHRBE(r, n)		(0x7c00025c | __PPC_RT(r) | (((n) & 0x3ff) << 11))
460  #define PPC_RAW_TRECHKPT		(PPC_INST_TRECHKPT)
461  #define PPC_RAW_TRECLAIM(r)		(PPC_INST_TRECLAIM | __PPC_RA(r))
462  #define PPC_RAW_TABORT(r)		(0x7c00071d | __PPC_RA(r))
463  #define TMRN(x)				((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
464  #define PPC_RAW_MTTMR(tmr, r)		(0x7c0003dc | TMRN(tmr) | ___PPC_RS(r))
465  #define PPC_RAW_MFTMR(tmr, r)		(0x7c0002dc | TMRN(tmr) | ___PPC_RT(r))
466  #define PPC_RAW_ICSWX(s, a, b)		(0x7c00032d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
467  #define PPC_RAW_ICSWEPX(s, a, b)	(0x7c00076d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
468  #define PPC_RAW_SLBIA(IH)		(0x7c0003e4 | (((IH) & 0x7) << 21))
469  #define PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb) \
470  	(0x100000c7 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
471  #define PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb) \
472  	(0x10000006 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
473  #define PPC_RAW_LD(r, base, i)		(0xe8000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
474  #define PPC_RAW_LWA(r, base, i)		(0xe8000002 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
475  #define PPC_RAW_LWZ(r, base, i)		(0x80000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
476  #define PPC_RAW_LWZX(t, a, b)		(0x7c00002e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
477  #define PPC_RAW_STD(r, base, i)		(0xf8000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_DS(i))
478  #define PPC_RAW_STDCX(s, a, b)		(0x7c0001ad | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
479  #define PPC_RAW_LFSX(t, a, b)		(0x7c00042e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
480  #define PPC_RAW_STFSX(s, a, b)		(0x7c00052e | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
481  #define PPC_RAW_LFDX(t, a, b)		(0x7c0004ae | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
482  #define PPC_RAW_STFDX(s, a, b)		(0x7c0005ae | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
483  #define PPC_RAW_LVX(t, a, b)		(0x7c0000ce | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
484  #define PPC_RAW_STVX(s, a, b)		(0x7c0001ce | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
485  #define PPC_RAW_ADDE(t, a, b)		(0x7c000114 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
486  #define PPC_RAW_ADDZE(t, a)		(0x7c000194 | ___PPC_RT(t) | ___PPC_RA(a))
487  #define PPC_RAW_ADDME(t, a)		(0x7c0001d4 | ___PPC_RT(t) | ___PPC_RA(a))
488  #define PPC_RAW_ADD(t, a, b)		(0x7c000214 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
489  #define PPC_RAW_ADD_DOT(t, a, b)	(0x7c000214 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
490  #define PPC_RAW_ADDC(t, a, b)		(0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
491  #define PPC_RAW_ADDC_DOT(t, a, b)	(0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
492  #define PPC_RAW_NOP()			PPC_RAW_ORI(0, 0, 0)
493  #define PPC_RAW_BLR()			(0x4e800020)
494  #define PPC_RAW_BLRL()			(0x4e800021)
495  #define PPC_RAW_MTLR(r)			(0x7c0803a6 | ___PPC_RT(r))
496  #define PPC_RAW_MFLR(t)			(0x7c0802a6 | ___PPC_RT(t))
497  #define PPC_RAW_BCTR()			(0x4e800420)
498  #define PPC_RAW_BCTRL()			(0x4e800421)
499  #define PPC_RAW_MTCTR(r)		(0x7c0903a6 | ___PPC_RT(r))
500  #define PPC_RAW_ADDI(d, a, i)		(0x38000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
501  #define PPC_RAW_LI(r, i)		PPC_RAW_ADDI(r, 0, i)
502  #define PPC_RAW_ADDIS(d, a, i)		(0x3c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
503  #define PPC_RAW_ADDIC(d, a, i)		(0x30000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
504  #define PPC_RAW_ADDIC_DOT(d, a, i)	(0x34000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
505  #define PPC_RAW_LIS(r, i)		PPC_RAW_ADDIS(r, 0, i)
506  #define PPC_RAW_STDX(r, base, b)	(0x7c00012a | ___PPC_RS(r) | ___PPC_RA(base) | ___PPC_RB(b))
507  #define PPC_RAW_STDU(r, base, i)	(0xf8000001 | ___PPC_RS(r) | ___PPC_RA(base) | ((i) & 0xfffc))
508  #define PPC_RAW_STW(r, base, i)		(0x90000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
509  #define PPC_RAW_STWU(r, base, i)	(0x94000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
510  #define PPC_RAW_STH(r, base, i)		(0xb0000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
511  #define PPC_RAW_STB(r, base, i)		(0x98000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
512  #define PPC_RAW_LBZ(r, base, i)		(0x88000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
513  #define PPC_RAW_LDX(r, base, b)		(0x7c00002a | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
514  #define PPC_RAW_LHA(r, base, i)		(0xa8000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
515  #define PPC_RAW_LHZ(r, base, i)		(0xa0000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
516  #define PPC_RAW_LHBRX(r, base, b)	(0x7c00062c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
517  #define PPC_RAW_LWBRX(r, base, b)	(0x7c00042c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
518  #define PPC_RAW_LDBRX(r, base, b)	(0x7c000428 | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
519  #define PPC_RAW_STWCX(s, a, b)		(0x7c00012d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
520  #define PPC_RAW_CMPWI(a, i)		(0x2c000000 | ___PPC_RA(a) | IMM_L(i))
521  #define PPC_RAW_CMPDI(a, i)		(0x2c200000 | ___PPC_RA(a) | IMM_L(i))
522  #define PPC_RAW_CMPW(a, b)		(0x7c000000 | ___PPC_RA(a) | ___PPC_RB(b))
523  #define PPC_RAW_CMPD(a, b)		(0x7c200000 | ___PPC_RA(a) | ___PPC_RB(b))
524  #define PPC_RAW_CMPLWI(a, i)		(0x28000000 | ___PPC_RA(a) | IMM_L(i))
525  #define PPC_RAW_CMPLDI(a, i)		(0x28200000 | ___PPC_RA(a) | IMM_L(i))
526  #define PPC_RAW_CMPLW(a, b)		(0x7c000040 | ___PPC_RA(a) | ___PPC_RB(b))
527  #define PPC_RAW_CMPLD(a, b)		(0x7c200040 | ___PPC_RA(a) | ___PPC_RB(b))
528  #define PPC_RAW_SUB(d, a, b)		(0x7c000050 | ___PPC_RT(d) | ___PPC_RB(a) | ___PPC_RA(b))
529  #define PPC_RAW_SUBFC(d, a, b)		(0x7c000010 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
530  #define PPC_RAW_SUBFE(d, a, b)		(0x7c000110 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
531  #define PPC_RAW_SUBFIC(d, a, i)		(0x20000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
532  #define PPC_RAW_SUBFZE(d, a)		(0x7c000190 | ___PPC_RT(d) | ___PPC_RA(a))
533  #define PPC_RAW_MULD(d, a, b)		(0x7c0001d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
534  #define PPC_RAW_MULW(d, a, b)		(0x7c0001d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
535  #define PPC_RAW_MULHWU(d, a, b)		(0x7c000016 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
536  #define PPC_RAW_MULI(d, a, i)		(0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
537  #define PPC_RAW_DIVW(d, a, b)		(0x7c0003d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
538  #define PPC_RAW_DIVWU(d, a, b)		(0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
539  #define PPC_RAW_DIVD(d, a, b)		(0x7c0003d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
540  #define PPC_RAW_DIVDU(d, a, b)		(0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
541  #define PPC_RAW_DIVDE(t, a, b)		(0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
542  #define PPC_RAW_DIVDE_DOT(t, a, b)	(0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
543  #define PPC_RAW_DIVDEU(t, a, b)		(0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
544  #define PPC_RAW_DIVDEU_DOT(t, a, b)	(0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
545  #define PPC_RAW_AND(d, a, b)		(0x7c000038 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
546  #define PPC_RAW_ANDI(d, a, i)		(0x70000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
547  #define PPC_RAW_ANDIS(d, a, i)		(0x74000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
548  #define PPC_RAW_AND_DOT(d, a, b)	(0x7c000039 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
549  #define PPC_RAW_OR(d, a, b)		(0x7c000378 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
550  #define PPC_RAW_MR(d, a)		PPC_RAW_OR(d, a, a)
551  #define PPC_RAW_ORI(d, a, i)		(0x60000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
552  #define PPC_RAW_ORIS(d, a, i)		(0x64000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
553  #define PPC_RAW_NOR(d, a, b)		(0x7c0000f8 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
554  #define PPC_RAW_XOR(d, a, b)		(0x7c000278 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
555  #define PPC_RAW_XORI(d, a, i)		(0x68000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
556  #define PPC_RAW_XORIS(d, a, i)		(0x6c000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
557  #define PPC_RAW_EXTSB(d, a)		(0x7c000774 | ___PPC_RA(d) | ___PPC_RS(a))
558  #define PPC_RAW_EXTSH(d, a)		(0x7c000734 | ___PPC_RA(d) | ___PPC_RS(a))
559  #define PPC_RAW_EXTSW(d, a)		(0x7c0007b4 | ___PPC_RA(d) | ___PPC_RS(a))
560  #define PPC_RAW_SLW(d, a, s)		(0x7c000030 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
561  #define PPC_RAW_SLD(d, a, s)		(0x7c000036 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
562  #define PPC_RAW_SRW(d, a, s)		(0x7c000430 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
563  #define PPC_RAW_SRAW(d, a, s)		(0x7c000630 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
564  #define PPC_RAW_SRAWI(d, a, i)		(0x7c000670 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i))
565  #define PPC_RAW_SRD(d, a, s)		(0x7c000436 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
566  #define PPC_RAW_SRAD(d, a, s)		(0x7c000634 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
567  #define PPC_RAW_SRADI(d, a, i)		(0x7c000674 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i))
568  #define PPC_RAW_RLWINM(d, a, i, mb, me)	(0x54000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
569  #define PPC_RAW_RLWINM_DOT(d, a, i, mb, me) \
570  					(0x54000001 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
571  #define PPC_RAW_RLWIMI(d, a, i, mb, me) (0x50000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
572  #define PPC_RAW_RLDICL(d, a, i, mb)     (0x78000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_MB64(mb))
573  #define PPC_RAW_RLDICR(d, a, i, me)     (0x78000004 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_ME64(me))
574  
575  /* slwi = rlwinm Rx, Ry, n, 0, 31-n */
576  #define PPC_RAW_SLWI(d, a, i)		PPC_RAW_RLWINM(d, a, i, 0, 31-(i))
577  /* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
578  #define PPC_RAW_SRWI(d, a, i)		PPC_RAW_RLWINM(d, a, 32-(i), i, 31)
579  /* sldi = rldicr Rx, Ry, n, 63-n */
580  #define PPC_RAW_SLDI(d, a, i)		PPC_RAW_RLDICR(d, a, i, 63-(i))
581  /* sldi = rldicl Rx, Ry, 64-n, n */
582  #define PPC_RAW_SRDI(d, a, i)		PPC_RAW_RLDICL(d, a, 64-(i), i)
583  
584  #define PPC_RAW_NEG(d, a)		(0x7c0000d0 | ___PPC_RT(d) | ___PPC_RA(a))
585  
586  #define PPC_RAW_MFSPR(d, spr)		(0x7c0002a6 | ___PPC_RT(d) | __PPC_SPR(spr))
587  #define PPC_RAW_MTSPR(spr, d)		(0x7c0003a6 | ___PPC_RS(d) | __PPC_SPR(spr))
588  #define PPC_RAW_EIEIO()			(0x7c0006ac)
589  
590  #define PPC_RAW_BRANCH(offset)		(0x48000000 | PPC_LI(offset))
591  #define PPC_RAW_BL(offset)		(0x48000001 | PPC_LI(offset))
592  #define PPC_RAW_TW(t0, a, b)		(0x7c000008 | ___PPC_RS(t0) | ___PPC_RA(a) | ___PPC_RB(b))
593  #define PPC_RAW_TRAP()			PPC_RAW_TW(31, 0, 0)
594  #define PPC_RAW_SETB(t, bfa)		(0x7c000100 | ___PPC_RT(t) | ___PPC_RA((bfa) << 2))
595  
596  /* Deal with instructions that older assemblers aren't aware of */
597  #define	PPC_BCCTR_FLUSH		stringify_in_c(.long PPC_INST_BCCTR_FLUSH)
598  #define	PPC_CP_ABORT		stringify_in_c(.long PPC_RAW_CP_ABORT)
599  #define	PPC_COPY(a, b)		stringify_in_c(.long PPC_RAW_COPY(a, b))
600  #define PPC_DARN(t, l)		stringify_in_c(.long PPC_RAW_DARN(t, l))
601  #define	PPC_DCBAL(a, b)		stringify_in_c(.long PPC_RAW_DCBAL(a, b))
602  #define	PPC_DCBZL(a, b)		stringify_in_c(.long PPC_RAW_DCBZL(a, b))
603  #define	PPC_DIVDE(t, a, b)	stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
604  #define	PPC_DIVDEU(t, a, b)	stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
605  #define PPC_DSSALL		stringify_in_c(.long PPC_INST_DSSALL)
606  #define PPC_LQARX(t, a, b, eh)	stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
607  #define PPC_STQCX(t, a, b)	stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
608  #define PPC_MADDHD(t, a, b, c)	stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))
609  #define PPC_MADDHDU(t, a, b, c)	stringify_in_c(.long PPC_RAW_MADDHDU(t, a, b, c))
610  #define PPC_MADDLD(t, a, b, c)	stringify_in_c(.long PPC_RAW_MADDLD(t, a, b, c))
611  #define PPC_MSGSND(b)		stringify_in_c(.long PPC_RAW_MSGSND(b))
612  #define PPC_MSGSYNC		stringify_in_c(.long PPC_RAW_MSGSYNC)
613  #define PPC_MSGCLR(b)		stringify_in_c(.long PPC_RAW_MSGCLR(b))
614  #define PPC_MSGSNDP(b)		stringify_in_c(.long PPC_RAW_MSGSNDP(b))
615  #define PPC_MSGCLRP(b)		stringify_in_c(.long PPC_RAW_MSGCLRP(b))
616  #define PPC_PASTE(a, b)		stringify_in_c(.long PPC_RAW_PASTE(a, b))
617  #define PPC_POPCNTB(a, s)	stringify_in_c(.long PPC_RAW_POPCNTB(a, s))
618  #define PPC_POPCNTD(a, s)	stringify_in_c(.long PPC_RAW_POPCNTD(a, s))
619  #define PPC_POPCNTW(a, s)	stringify_in_c(.long PPC_RAW_POPCNTW(a, s))
620  #define PPC_RFCI		stringify_in_c(.long PPC_RAW_RFCI)
621  #define PPC_RFDI		stringify_in_c(.long PPC_RAW_RFDI)
622  #define PPC_RFMCI		stringify_in_c(.long PPC_RAW_RFMCI)
623  #define PPC_TLBILX(t, a, b)	stringify_in_c(.long PPC_RAW_TLBILX(t, a, b))
624  #define PPC_TLBILX_ALL(a, b)	PPC_TLBILX(0, a, b)
625  #define PPC_TLBILX_PID(a, b)	PPC_TLBILX(1, a, b)
626  #define PPC_TLBILX_LPID		stringify_in_c(.long PPC_RAW_TLBILX_LPID)
627  #define PPC_TLBILX_VA(a, b)	PPC_TLBILX(3, a, b)
628  #define PPC_WAIT_v203		stringify_in_c(.long PPC_RAW_WAIT_v203)
629  #define PPC_WAIT(w, p)		stringify_in_c(.long PPC_RAW_WAIT(w, p))
630  #define PPC_TLBIE(lp, a) 	stringify_in_c(.long PPC_RAW_TLBIE(lp, a))
631  #define	PPC_TLBIE_5(rb, rs, ric, prs, r) \
632  				stringify_in_c(.long PPC_RAW_TLBIE_5(rb, rs, ric, prs, r))
633  #define	PPC_TLBIEL(rb,rs,ric,prs,r) \
634  				stringify_in_c(.long PPC_RAW_TLBIEL(rb, rs, ric, prs, r))
635  #define PPC_TLBIEL_v205(rb, l)	stringify_in_c(.long PPC_RAW_TLBIEL_v205(rb, l))
636  #define PPC_TLBSRX_DOT(a, b)	stringify_in_c(.long PPC_RAW_TLBSRX_DOT(a, b))
637  #define PPC_TLBIVAX(a, b)	stringify_in_c(.long PPC_RAW_TLBIVAX(a, b))
638  
639  #define PPC_ERATWE(s, a, w)	stringify_in_c(.long PPC_RAW_ERATWE(s, a, w))
640  #define PPC_ERATRE(s, a, w)	stringify_in_c(.long PPC_RAW_ERATRE(a, a, w))
641  #define PPC_ERATILX(t, a, b)	stringify_in_c(.long PPC_RAW_ERATILX(t, a, b))
642  #define PPC_ERATIVAX(s, a, b)	stringify_in_c(.long PPC_RAW_ERATIVAX(s, a, b))
643  #define PPC_ERATSX(t, a, w)	stringify_in_c(.long PPC_RAW_ERATSX(t, a, w))
644  #define PPC_ERATSX_DOT(t, a, w)	stringify_in_c(.long PPC_RAW_ERATSX_DOT(t, a, w))
645  #define PPC_SLBFEE_DOT(t, b)	stringify_in_c(.long PPC_RAW_SLBFEE_DOT(t, b))
646  #define __PPC_SLBFEE_DOT(t, b)	stringify_in_c(.long __PPC_RAW_SLBFEE_DOT(t, b))
647  #define PPC_ICBT(c, a, b)	stringify_in_c(.long PPC_RAW_ICBT(c, a, b))
648  /* PASemi instructions */
649  #define LBZCIX(t, a, b)		stringify_in_c(.long PPC_RAW_LBZCIX(t, a, b))
650  #define STBCIX(s, a, b)		stringify_in_c(.long PPC_RAW_STBCIX(s, a, b))
651  #define PPC_DCBFPS(a, b)	stringify_in_c(.long PPC_RAW_DCBFPS(a, b))
652  #define PPC_DCBSTPS(a, b)	stringify_in_c(.long PPC_RAW_DCBSTPS(a, b))
653  #define PPC_PHWSYNC		stringify_in_c(.long PPC_RAW_PHWSYNC)
654  #define PPC_PLWSYNC		stringify_in_c(.long PPC_RAW_PLWSYNC)
655  #define STXVD2X(s, a, b)	stringify_in_c(.long PPC_RAW_STXVD2X(s, a, b))
656  #define LXVD2X(s, a, b)		stringify_in_c(.long PPC_RAW_LXVD2X(s, a, b))
657  #define MFVRD(a, t)		stringify_in_c(.long PPC_RAW_MFVRD(a, t))
658  #define MTVRD(t, a)		stringify_in_c(.long PPC_RAW_MTVRD(t, a))
659  #define VPMSUMW(t, a, b)	stringify_in_c(.long PPC_RAW_VPMSUMW(t, a, b))
660  #define VPMSUMD(t, a, b)	stringify_in_c(.long PPC_RAW_VPMSUMD(t, a, b))
661  #define XXLOR(t, a, b)		stringify_in_c(.long PPC_RAW_XXLOR(t, a, b))
662  #define XXSWAPD(t, a)		stringify_in_c(.long PPC_RAW_XXSWAPD(t, a))
663  #define XVCPSGNDP(t, a, b)	stringify_in_c(.long (PPC_RAW_XVCPSGNDP(t, a, b)))
664  
665  #define VPERMXOR(vrt, vra, vrb, vrc)				\
666  	stringify_in_c(.long (PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc)))
667  
668  #define PPC_NAP			stringify_in_c(.long PPC_RAW_NAP)
669  #define PPC_SLEEP		stringify_in_c(.long PPC_RAW_SLEEP)
670  #define PPC_WINKLE		stringify_in_c(.long PPC_RAW_WINKLE)
671  
672  #define PPC_STOP		stringify_in_c(.long PPC_RAW_STOP)
673  
674  /* BHRB instructions */
675  #define PPC_CLRBHRB		stringify_in_c(.long PPC_RAW_CLRBHRB)
676  #define PPC_MFBHRBE(r, n)	stringify_in_c(.long PPC_RAW_MFBHRBE(r, n))
677  
678  /* Transactional memory instructions */
679  #define TRECHKPT		stringify_in_c(.long PPC_RAW_TRECHKPT)
680  #define TRECLAIM(r)		stringify_in_c(.long PPC_RAW_TRECLAIM(r))
681  #define TABORT(r)		stringify_in_c(.long PPC_RAW_TABORT(r))
682  
683  /* book3e thread control instructions */
684  #define MTTMR(tmr, r)		stringify_in_c(.long PPC_RAW_MTTMR(tmr, r))
685  #define MFTMR(tmr, r)		stringify_in_c(.long PPC_RAW_MFTMR(tmr, r))
686  
687  /* Coprocessor instructions */
688  #define PPC_ICSWX(s, a, b)	stringify_in_c(.long PPC_RAW_ICSWX(s, a, b))
689  #define PPC_ICSWEPX(s, a, b)	stringify_in_c(.long PPC_RAW_ICSWEPX(s, a, b))
690  
691  #define PPC_SLBIA(IH)	stringify_in_c(.long PPC_RAW_SLBIA(IH))
692  
693  /*
694   * These may only be used on ISA v3.0 or later (aka. CPU_FTR_ARCH_300, radix
695   * implies CPU_FTR_ARCH_300). USER/GUEST invalidates may only be used by radix
696   * mode (on HPT these would also invalidate various SLBEs which may not be
697   * desired).
698   */
699  #define PPC_ISA_3_0_INVALIDATE_ERAT	PPC_SLBIA(7)
700  #define PPC_RADIX_INVALIDATE_ERAT_USER	PPC_SLBIA(3)
701  #define PPC_RADIX_INVALIDATE_ERAT_GUEST	PPC_SLBIA(6)
702  
703  #define VCMPEQUD_RC(vrt, vra, vrb)	stringify_in_c(.long PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb))
704  
705  #define VCMPEQUB_RC(vrt, vra, vrb)	stringify_in_c(.long PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb))
706  
707  #endif /* _ASM_POWERPC_PPC_OPCODE_H */
708