1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 7 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8) 55 56 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 57 KVM_DIRTY_LOG_INITIALLY_SET) 58 59 #define KVM_HAVE_MMU_RWLOCK 60 61 /* 62 * Mode of operation configurable with kvm-arm.mode early param. 63 * See Documentation/admin-guide/kernel-parameters.txt for more information. 64 */ 65 enum kvm_mode { 66 KVM_MODE_DEFAULT, 67 KVM_MODE_PROTECTED, 68 KVM_MODE_NV, 69 KVM_MODE_NONE, 70 }; 71 #ifdef CONFIG_KVM 72 enum kvm_mode kvm_get_mode(void); 73 #else kvm_get_mode(void)74 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 75 #endif 76 77 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 78 79 extern unsigned int __ro_after_init kvm_sve_max_vl; 80 extern unsigned int __ro_after_init kvm_host_sve_max_vl; 81 int __init kvm_arm_init_sve(void); 82 83 u32 __attribute_const__ kvm_target_cpu(void); 84 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 85 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 86 87 struct kvm_hyp_memcache { 88 phys_addr_t head; 89 unsigned long nr_pages; 90 }; 91 push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt))92 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 93 phys_addr_t *p, 94 phys_addr_t (*to_pa)(void *virt)) 95 { 96 *p = mc->head; 97 mc->head = to_pa(p); 98 mc->nr_pages++; 99 } 100 pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys))101 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 102 void *(*to_va)(phys_addr_t phys)) 103 { 104 phys_addr_t *p = to_va(mc->head); 105 106 if (!mc->nr_pages) 107 return NULL; 108 109 mc->head = *p; 110 mc->nr_pages--; 111 112 return p; 113 } 114 __topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg),phys_addr_t (* to_pa)(void * virt),void * arg)115 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 116 unsigned long min_pages, 117 void *(*alloc_fn)(void *arg), 118 phys_addr_t (*to_pa)(void *virt), 119 void *arg) 120 { 121 while (mc->nr_pages < min_pages) { 122 phys_addr_t *p = alloc_fn(arg); 123 124 if (!p) 125 return -ENOMEM; 126 push_hyp_memcache(mc, p, to_pa); 127 } 128 129 return 0; 130 } 131 __free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg),void * (* to_va)(phys_addr_t phys),void * arg)132 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 133 void (*free_fn)(void *virt, void *arg), 134 void *(*to_va)(phys_addr_t phys), 135 void *arg) 136 { 137 while (mc->nr_pages) 138 free_fn(pop_hyp_memcache(mc, to_va), arg); 139 } 140 141 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 142 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 143 144 struct kvm_vmid { 145 atomic64_t id; 146 }; 147 148 struct kvm_s2_mmu { 149 struct kvm_vmid vmid; 150 151 /* 152 * stage2 entry level table 153 * 154 * Two kvm_s2_mmu structures in the same VM can point to the same 155 * pgd here. This happens when running a guest using a 156 * translation regime that isn't affected by its own stage-2 157 * translation, such as a non-VHE hypervisor running at vEL2, or 158 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 159 * canonical stage-2 page tables. 160 */ 161 phys_addr_t pgd_phys; 162 struct kvm_pgtable *pgt; 163 164 /* 165 * VTCR value used on the host. For a non-NV guest (or a NV 166 * guest that runs in a context where its own S2 doesn't 167 * apply), its T0SZ value reflects that of the IPA size. 168 * 169 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 170 * the guest. 171 */ 172 u64 vtcr; 173 174 /* The last vcpu id that ran on each physical CPU */ 175 int __percpu *last_vcpu_ran; 176 177 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 178 /* 179 * Memory cache used to split 180 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 181 * is used to allocate stage2 page tables while splitting huge 182 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 183 * influences both the capacity of the split page cache, and 184 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 185 * too high. 186 * 187 * Protected by kvm->slots_lock. 188 */ 189 struct kvm_mmu_memory_cache split_page_cache; 190 uint64_t split_page_chunk_size; 191 192 struct kvm_arch *arch; 193 194 /* 195 * For a shadow stage-2 MMU, the virtual vttbr used by the 196 * host to parse the guest S2. 197 * This either contains: 198 * - the virtual VTTBR programmed by the guest hypervisor with 199 * CnP cleared 200 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 201 * 202 * We also cache the full VTCR which gets used for TLB invalidation, 203 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted 204 * to be cached in a TLB" to the letter. 205 */ 206 u64 tlb_vttbr; 207 u64 tlb_vtcr; 208 209 /* 210 * true when this represents a nested context where virtual 211 * HCR_EL2.VM == 1 212 */ 213 bool nested_stage2_enabled; 214 215 /* 216 * true when this MMU needs to be unmapped before being used for a new 217 * purpose. 218 */ 219 bool pending_unmap; 220 221 /* 222 * 0: Nobody is currently using this, check vttbr for validity 223 * >0: Somebody is actively using this. 224 */ 225 atomic_t refcnt; 226 }; 227 228 struct kvm_arch_memory_slot { 229 }; 230 231 /** 232 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 233 * 234 * @std_bmap: Bitmap of standard secure service calls 235 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 236 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 237 */ 238 struct kvm_smccc_features { 239 unsigned long std_bmap; 240 unsigned long std_hyp_bmap; 241 unsigned long vendor_hyp_bmap; 242 }; 243 244 typedef unsigned int pkvm_handle_t; 245 246 struct kvm_protected_vm { 247 pkvm_handle_t handle; 248 struct kvm_hyp_memcache teardown_mc; 249 bool enabled; 250 }; 251 252 struct kvm_mpidr_data { 253 u64 mpidr_mask; 254 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 255 }; 256 kvm_mpidr_index(struct kvm_mpidr_data * data,u64 mpidr)257 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 258 { 259 unsigned long index = 0, mask = data->mpidr_mask; 260 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 261 262 bitmap_gather(&index, &aff, &mask, fls(mask)); 263 264 return index; 265 } 266 267 struct kvm_sysreg_masks; 268 269 enum fgt_group_id { 270 __NO_FGT_GROUP__, 271 HFGxTR_GROUP, 272 HDFGRTR_GROUP, 273 HDFGWTR_GROUP = HDFGRTR_GROUP, 274 HFGITR_GROUP, 275 HAFGRTR_GROUP, 276 277 /* Must be last */ 278 __NR_FGT_GROUP_IDS__ 279 }; 280 281 struct kvm_arch { 282 struct kvm_s2_mmu mmu; 283 284 /* 285 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 286 * architecture. We track them globally, as we present the 287 * same feature-set to all vcpus. 288 * 289 * Index 0 is currently spare. 290 */ 291 u64 fgu[__NR_FGT_GROUP_IDS__]; 292 293 /* 294 * Stage 2 paging state for VMs with nested S2 using a virtual 295 * VMID. 296 */ 297 struct kvm_s2_mmu *nested_mmus; 298 size_t nested_mmus_size; 299 int nested_mmus_next; 300 301 /* Interrupt controller */ 302 struct vgic_dist vgic; 303 304 /* Timers */ 305 struct arch_timer_vm_data timer_data; 306 307 /* Mandated version of PSCI */ 308 u32 psci_version; 309 310 /* Protects VM-scoped configuration data */ 311 struct mutex config_lock; 312 313 /* 314 * If we encounter a data abort without valid instruction syndrome 315 * information, report this to user space. User space can (and 316 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 317 * supported. 318 */ 319 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 320 /* Memory Tagging Extension enabled for the guest */ 321 #define KVM_ARCH_FLAG_MTE_ENABLED 1 322 /* At least one vCPU has ran in the VM */ 323 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 324 /* The vCPU feature set for the VM is configured */ 325 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 326 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 327 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 328 /* VM counter offset */ 329 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 330 /* Timer PPIs made immutable */ 331 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 332 /* Initial ID reg values loaded */ 333 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 334 /* Fine-Grained UNDEF initialised */ 335 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 336 unsigned long flags; 337 338 /* VM-wide vCPU feature set */ 339 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 340 341 /* MPIDR to vcpu index mapping, optional */ 342 struct kvm_mpidr_data *mpidr_data; 343 344 /* 345 * VM-wide PMU filter, implemented as a bitmap and big enough for 346 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 347 */ 348 unsigned long *pmu_filter; 349 struct arm_pmu *arm_pmu; 350 351 cpumask_var_t supported_cpus; 352 353 /* PMCR_EL0.N value for the guest */ 354 u8 pmcr_n; 355 356 /* Iterator for idreg debugfs */ 357 u8 idreg_debugfs_iter; 358 359 /* Hypercall features firmware registers' descriptor */ 360 struct kvm_smccc_features smccc_feat; 361 struct maple_tree smccc_filter; 362 363 /* 364 * Emulated CPU ID registers per VM 365 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 366 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 367 * 368 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 369 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 370 */ 371 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 372 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 373 u64 id_regs[KVM_ARM_ID_REG_NUM]; 374 375 u64 ctr_el0; 376 377 /* Masks for VNCR-baked sysregs */ 378 struct kvm_sysreg_masks *sysreg_masks; 379 380 /* 381 * For an untrusted host VM, 'pkvm.handle' is used to lookup 382 * the associated pKVM instance in the hypervisor. 383 */ 384 struct kvm_protected_vm pkvm; 385 }; 386 387 struct kvm_vcpu_fault_info { 388 u64 esr_el2; /* Hyp Syndrom Register */ 389 u64 far_el2; /* Hyp Fault Address Register */ 390 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 391 u64 disr_el1; /* Deferred [SError] Status Register */ 392 }; 393 394 /* 395 * VNCR() just places the VNCR_capable registers in the enum after 396 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 397 * from the VNCR base. As we don't require the enum to be otherwise ordered, 398 * we need the terrible hack below to ensure that we correctly size the 399 * sys_regs array, no matter what. 400 * 401 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 402 * treasure trove of bit hacks: 403 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 404 */ 405 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 406 #define VNCR(r) \ 407 __before_##r, \ 408 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 409 __after_##r = __MAX__(__before_##r - 1, r) 410 411 enum vcpu_sysreg { 412 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 413 MPIDR_EL1, /* MultiProcessor Affinity Register */ 414 CLIDR_EL1, /* Cache Level ID Register */ 415 CSSELR_EL1, /* Cache Size Selection Register */ 416 TPIDR_EL0, /* Thread ID, User R/W */ 417 TPIDRRO_EL0, /* Thread ID, User R/O */ 418 TPIDR_EL1, /* Thread ID, Privileged */ 419 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 420 PAR_EL1, /* Physical Address Register */ 421 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 422 OSLSR_EL1, /* OS Lock Status Register */ 423 DISR_EL1, /* Deferred Interrupt Status Register */ 424 425 /* Performance Monitors Registers */ 426 PMCR_EL0, /* Control Register */ 427 PMSELR_EL0, /* Event Counter Selection Register */ 428 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 429 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 430 PMCCNTR_EL0, /* Cycle Counter Register */ 431 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 432 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 433 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 434 PMCNTENSET_EL0, /* Count Enable Set Register */ 435 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 436 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 437 PMUSERENR_EL0, /* User Enable Register */ 438 439 /* Pointer Authentication Registers in a strict increasing order. */ 440 APIAKEYLO_EL1, 441 APIAKEYHI_EL1, 442 APIBKEYLO_EL1, 443 APIBKEYHI_EL1, 444 APDAKEYLO_EL1, 445 APDAKEYHI_EL1, 446 APDBKEYLO_EL1, 447 APDBKEYHI_EL1, 448 APGAKEYLO_EL1, 449 APGAKEYHI_EL1, 450 451 /* Memory Tagging Extension registers */ 452 RGSR_EL1, /* Random Allocation Tag Seed Register */ 453 GCR_EL1, /* Tag Control Register */ 454 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 455 456 POR_EL0, /* Permission Overlay Register 0 (EL0) */ 457 458 /* FP/SIMD/SVE */ 459 SVCR, 460 FPMR, 461 462 /* 32bit specific registers. */ 463 DACR32_EL2, /* Domain Access Control Register */ 464 IFSR32_EL2, /* Instruction Fault Status Register */ 465 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 466 DBGVCR32_EL2, /* Debug Vector Catch Register */ 467 468 /* EL2 registers */ 469 SCTLR_EL2, /* System Control Register (EL2) */ 470 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 471 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 472 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 473 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 474 ZCR_EL2, /* SVE Control Register (EL2) */ 475 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 476 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 477 TCR_EL2, /* Translation Control Register (EL2) */ 478 SPSR_EL2, /* EL2 saved program status register */ 479 ELR_EL2, /* EL2 exception link register */ 480 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 481 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 482 ESR_EL2, /* Exception Syndrome Register (EL2) */ 483 FAR_EL2, /* Fault Address Register (EL2) */ 484 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 485 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 486 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 487 VBAR_EL2, /* Vector Base Address Register (EL2) */ 488 RVBAR_EL2, /* Reset Vector Base Address Register */ 489 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 490 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 491 SP_EL2, /* EL2 Stack Pointer */ 492 CNTHP_CTL_EL2, 493 CNTHP_CVAL_EL2, 494 CNTHV_CTL_EL2, 495 CNTHV_CVAL_EL2, 496 497 __VNCR_START__, /* Any VNCR-capable reg goes after this point */ 498 499 VNCR(SCTLR_EL1),/* System Control Register */ 500 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 501 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 502 VNCR(ZCR_EL1), /* SVE Control */ 503 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 504 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 505 VNCR(TCR_EL1), /* Translation Control Register */ 506 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 507 VNCR(ESR_EL1), /* Exception Syndrome Register */ 508 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 509 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 510 VNCR(FAR_EL1), /* Fault Address Register */ 511 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 512 VNCR(VBAR_EL1), /* Vector Base Address Register */ 513 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 514 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 515 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 516 VNCR(ELR_EL1), 517 VNCR(SP_EL1), 518 VNCR(SPSR_EL1), 519 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 520 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 521 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 522 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 523 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 524 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 525 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 526 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 527 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 528 529 /* Permission Indirection Extension registers */ 530 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 531 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 532 533 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ 534 535 VNCR(HFGRTR_EL2), 536 VNCR(HFGWTR_EL2), 537 VNCR(HFGITR_EL2), 538 VNCR(HDFGRTR_EL2), 539 VNCR(HDFGWTR_EL2), 540 VNCR(HAFGRTR_EL2), 541 542 VNCR(CNTVOFF_EL2), 543 VNCR(CNTV_CVAL_EL0), 544 VNCR(CNTV_CTL_EL0), 545 VNCR(CNTP_CVAL_EL0), 546 VNCR(CNTP_CTL_EL0), 547 548 VNCR(ICH_HCR_EL2), 549 550 NR_SYS_REGS /* Nothing after this line! */ 551 }; 552 553 struct kvm_sysreg_masks { 554 struct { 555 u64 res0; 556 u64 res1; 557 } mask[NR_SYS_REGS - __VNCR_START__]; 558 }; 559 560 struct kvm_cpu_context { 561 struct user_pt_regs regs; /* sp = sp_el0 */ 562 563 u64 spsr_abt; 564 u64 spsr_und; 565 u64 spsr_irq; 566 u64 spsr_fiq; 567 568 struct user_fpsimd_state fp_regs; 569 570 u64 sys_regs[NR_SYS_REGS]; 571 572 struct kvm_vcpu *__hyp_running_vcpu; 573 574 /* This pointer has to be 4kB aligned. */ 575 u64 *vncr_array; 576 }; 577 578 struct cpu_sve_state { 579 __u64 zcr_el1; 580 581 /* 582 * Ordering is important since __sve_save_state/__sve_restore_state 583 * relies on it. 584 */ 585 __u32 fpsr; 586 __u32 fpcr; 587 588 /* Must be SVE_VQ_BYTES (128 bit) aligned. */ 589 __u8 sve_regs[]; 590 }; 591 592 /* 593 * This structure is instantiated on a per-CPU basis, and contains 594 * data that is: 595 * 596 * - tied to a single physical CPU, and 597 * - either have a lifetime that does not extend past vcpu_put() 598 * - or is an invariant for the lifetime of the system 599 * 600 * Use host_data_ptr(field) as a way to access a pointer to such a 601 * field. 602 */ 603 struct kvm_host_data { 604 struct kvm_cpu_context host_ctxt; 605 606 /* 607 * All pointers in this union are hyp VA. 608 * sve_state is only used in pKVM and if system_supports_sve(). 609 */ 610 union { 611 struct user_fpsimd_state *fpsimd_state; 612 struct cpu_sve_state *sve_state; 613 }; 614 615 union { 616 /* HYP VA pointer to the host storage for FPMR */ 617 u64 *fpmr_ptr; 618 /* 619 * Used by pKVM only, as it needs to provide storage 620 * for the host 621 */ 622 u64 fpmr; 623 }; 624 625 /* Ownership of the FP regs */ 626 enum { 627 FP_STATE_FREE, 628 FP_STATE_HOST_OWNED, 629 FP_STATE_GUEST_OWNED, 630 } fp_owner; 631 632 /* 633 * host_debug_state contains the host registers which are 634 * saved and restored during world switches. 635 */ 636 struct { 637 /* {Break,watch}point registers */ 638 struct kvm_guest_debug_arch regs; 639 /* Statistical profiling extension */ 640 u64 pmscr_el1; 641 /* Self-hosted trace */ 642 u64 trfcr_el1; 643 /* Values of trap registers for the host before guest entry. */ 644 u64 mdcr_el2; 645 } host_debug_state; 646 }; 647 648 struct kvm_host_psci_config { 649 /* PSCI version used by host. */ 650 u32 version; 651 u32 smccc_version; 652 653 /* Function IDs used by host if version is v0.1. */ 654 struct psci_0_1_function_ids function_ids_0_1; 655 656 bool psci_0_1_cpu_suspend_implemented; 657 bool psci_0_1_cpu_on_implemented; 658 bool psci_0_1_cpu_off_implemented; 659 bool psci_0_1_migrate_implemented; 660 }; 661 662 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 663 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 664 665 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 666 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 667 668 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 669 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 670 671 struct vcpu_reset_state { 672 unsigned long pc; 673 unsigned long r0; 674 bool be; 675 bool reset; 676 }; 677 678 struct kvm_vcpu_arch { 679 struct kvm_cpu_context ctxt; 680 681 /* 682 * Guest floating point state 683 * 684 * The architecture has two main floating point extensions, 685 * the original FPSIMD and SVE. These have overlapping 686 * register views, with the FPSIMD V registers occupying the 687 * low 128 bits of the SVE Z registers. When the core 688 * floating point code saves the register state of a task it 689 * records which view it saved in fp_type. 690 */ 691 void *sve_state; 692 enum fp_type fp_type; 693 unsigned int sve_max_vl; 694 695 /* Stage 2 paging state used by the hardware on next switch */ 696 struct kvm_s2_mmu *hw_mmu; 697 698 /* Values of trap registers for the guest. */ 699 u64 hcr_el2; 700 u64 hcrx_el2; 701 u64 mdcr_el2; 702 u64 cptr_el2; 703 704 /* Exception Information */ 705 struct kvm_vcpu_fault_info fault; 706 707 /* Configuration flags, set once and for all before the vcpu can run */ 708 u8 cflags; 709 710 /* Input flags to the hypervisor code, potentially cleared after use */ 711 u8 iflags; 712 713 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 714 u8 sflags; 715 716 /* 717 * Don't run the guest (internal implementation need). 718 * 719 * Contrary to the flags above, this is set/cleared outside of 720 * a vcpu context, and thus cannot be mixed with the flags 721 * themselves (or the flag accesses need to be made atomic). 722 */ 723 bool pause; 724 725 /* 726 * We maintain more than a single set of debug registers to support 727 * debugging the guest from the host and to maintain separate host and 728 * guest state during world switches. vcpu_debug_state are the debug 729 * registers of the vcpu as the guest sees them. 730 * 731 * external_debug_state contains the debug values we want to debug the 732 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 733 * 734 * debug_ptr points to the set of debug registers that should be loaded 735 * onto the hardware when running the guest. 736 */ 737 struct kvm_guest_debug_arch *debug_ptr; 738 struct kvm_guest_debug_arch vcpu_debug_state; 739 struct kvm_guest_debug_arch external_debug_state; 740 741 /* VGIC state */ 742 struct vgic_cpu vgic_cpu; 743 struct arch_timer_cpu timer_cpu; 744 struct kvm_pmu pmu; 745 746 /* 747 * Guest registers we preserve during guest debugging. 748 * 749 * These shadow registers are updated by the kvm_handle_sys_reg 750 * trap handler if the guest accesses or updates them while we 751 * are using guest debug. 752 */ 753 struct { 754 u32 mdscr_el1; 755 bool pstate_ss; 756 } guest_debug_preserved; 757 758 /* vcpu power state */ 759 struct kvm_mp_state mp_state; 760 spinlock_t mp_state_lock; 761 762 /* Cache some mmu pages needed inside spinlock regions */ 763 struct kvm_mmu_memory_cache mmu_page_cache; 764 765 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 766 u64 vsesr_el2; 767 768 /* Additional reset state */ 769 struct vcpu_reset_state reset_state; 770 771 /* Guest PV state */ 772 struct { 773 u64 last_steal; 774 gpa_t base; 775 } steal; 776 777 /* Per-vcpu CCSIDR override or NULL */ 778 u32 *ccsidr; 779 }; 780 781 /* 782 * Each 'flag' is composed of a comma-separated triplet: 783 * 784 * - the flag-set it belongs to in the vcpu->arch structure 785 * - the value for that flag 786 * - the mask for that flag 787 * 788 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 789 * unpack_vcpu_flag() extract the flag value from the triplet for 790 * direct use outside of the flag accessors. 791 */ 792 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 793 794 #define __unpack_flag(_set, _f, _m) _f 795 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 796 797 #define __build_check_flag(v, flagset, f, m) \ 798 do { \ 799 typeof(v->arch.flagset) *_fset; \ 800 \ 801 /* Check that the flags fit in the mask */ \ 802 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 803 /* Check that the flags fit in the type */ \ 804 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 805 } while (0) 806 807 #define __vcpu_get_flag(v, flagset, f, m) \ 808 ({ \ 809 __build_check_flag(v, flagset, f, m); \ 810 \ 811 READ_ONCE(v->arch.flagset) & (m); \ 812 }) 813 814 /* 815 * Note that the set/clear accessors must be preempt-safe in order to 816 * avoid nesting them with load/put which also manipulate flags... 817 */ 818 #ifdef __KVM_NVHE_HYPERVISOR__ 819 /* the nVHE hypervisor is always non-preemptible */ 820 #define __vcpu_flags_preempt_disable() 821 #define __vcpu_flags_preempt_enable() 822 #else 823 #define __vcpu_flags_preempt_disable() preempt_disable() 824 #define __vcpu_flags_preempt_enable() preempt_enable() 825 #endif 826 827 #define __vcpu_set_flag(v, flagset, f, m) \ 828 do { \ 829 typeof(v->arch.flagset) *fset; \ 830 \ 831 __build_check_flag(v, flagset, f, m); \ 832 \ 833 fset = &v->arch.flagset; \ 834 __vcpu_flags_preempt_disable(); \ 835 if (HWEIGHT(m) > 1) \ 836 *fset &= ~(m); \ 837 *fset |= (f); \ 838 __vcpu_flags_preempt_enable(); \ 839 } while (0) 840 841 #define __vcpu_clear_flag(v, flagset, f, m) \ 842 do { \ 843 typeof(v->arch.flagset) *fset; \ 844 \ 845 __build_check_flag(v, flagset, f, m); \ 846 \ 847 fset = &v->arch.flagset; \ 848 __vcpu_flags_preempt_disable(); \ 849 *fset &= ~(m); \ 850 __vcpu_flags_preempt_enable(); \ 851 } while (0) 852 853 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 854 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 855 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 856 857 /* SVE exposed to guest */ 858 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0)) 859 /* SVE config completed */ 860 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 861 /* PTRAUTH exposed to guest */ 862 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2)) 863 /* KVM_ARM_VCPU_INIT completed */ 864 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(3)) 865 866 /* Exception pending */ 867 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 868 /* 869 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 870 * be set together with an exception... 871 */ 872 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 873 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 874 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 875 876 /* Helpers to encode exceptions with minimum fuss */ 877 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 878 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 879 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 880 881 /* 882 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 883 * values: 884 * 885 * For AArch32 EL1: 886 */ 887 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 888 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 889 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 890 /* For AArch64: */ 891 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 892 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 893 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 894 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 895 /* For AArch64 with NV: */ 896 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 897 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 898 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 899 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 900 /* Guest debug is live */ 901 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4)) 902 /* Save SPE context if active */ 903 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5)) 904 /* Save TRBE context if active */ 905 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) 906 907 /* SVE enabled for host EL0 */ 908 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) 909 /* SME enabled for EL0 */ 910 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1)) 911 /* Physical CPU not in supported_cpus */ 912 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2)) 913 /* WFIT instruction trapped */ 914 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3)) 915 /* vcpu system registers loaded on physical CPU */ 916 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4)) 917 /* Software step state is Active-pending */ 918 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5)) 919 /* PMUSERENR for the guest EL0 is on physical CPU */ 920 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6)) 921 /* WFI instruction trapped */ 922 #define IN_WFI __vcpu_single_flag(sflags, BIT(7)) 923 924 925 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 926 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 927 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 928 929 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 930 931 #define vcpu_sve_zcr_elx(vcpu) \ 932 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) 933 934 #define vcpu_sve_state_size(vcpu) ({ \ 935 size_t __size_ret; \ 936 unsigned int __vcpu_vq; \ 937 \ 938 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 939 __size_ret = 0; \ 940 } else { \ 941 __vcpu_vq = vcpu_sve_max_vq(vcpu); \ 942 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 943 } \ 944 \ 945 __size_ret; \ 946 }) 947 948 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 949 KVM_GUESTDBG_USE_SW_BP | \ 950 KVM_GUESTDBG_USE_HW | \ 951 KVM_GUESTDBG_SINGLESTEP) 952 953 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 954 vcpu_get_flag(vcpu, GUEST_HAS_SVE)) 955 956 #ifdef CONFIG_ARM64_PTR_AUTH 957 #define vcpu_has_ptrauth(vcpu) \ 958 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 959 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 960 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH)) 961 #else 962 #define vcpu_has_ptrauth(vcpu) false 963 #endif 964 965 #define vcpu_on_unsupported_cpu(vcpu) \ 966 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 967 968 #define vcpu_set_on_unsupported_cpu(vcpu) \ 969 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 970 971 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 972 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 973 974 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 975 976 /* 977 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 978 * memory backed version of a register, and not the one most recently 979 * accessed by a running VCPU. For example, for userspace access or 980 * for system registers that are never context switched, but only 981 * emulated. 982 * 983 * Don't bother with VNCR-based accesses in the nVHE code, it has no 984 * business dealing with NV. 985 */ ___ctxt_sys_reg(const struct kvm_cpu_context * ctxt,int r)986 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 987 { 988 #if !defined (__KVM_NVHE_HYPERVISOR__) 989 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 990 r >= __VNCR_START__ && ctxt->vncr_array)) 991 return &ctxt->vncr_array[r - __VNCR_START__]; 992 #endif 993 return (u64 *)&ctxt->sys_regs[r]; 994 } 995 996 #define __ctxt_sys_reg(c,r) \ 997 ({ \ 998 BUILD_BUG_ON(__builtin_constant_p(r) && \ 999 (r) >= NR_SYS_REGS); \ 1000 ___ctxt_sys_reg(c, r); \ 1001 }) 1002 1003 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 1004 1005 u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 1006 #define __vcpu_sys_reg(v,r) \ 1007 (*({ \ 1008 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1009 u64 *__r = __ctxt_sys_reg(ctxt, (r)); \ 1010 if (vcpu_has_nv((v)) && (r) >= __VNCR_START__) \ 1011 *__r = kvm_vcpu_sanitise_vncr_reg((v), (r)); \ 1012 __r; \ 1013 })) 1014 1015 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 1016 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 1017 __vcpu_read_sys_reg_from_cpu(int reg,u64 * val)1018 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 1019 { 1020 /* 1021 * *** VHE ONLY *** 1022 * 1023 * System registers listed in the switch are not saved on every 1024 * exit from the guest but are only saved on vcpu_put. 1025 * 1026 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 1027 * should never be listed below, because the guest cannot modify its 1028 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 1029 * thread when emulating cross-VCPU communication. 1030 */ 1031 if (!has_vhe()) 1032 return false; 1033 1034 switch (reg) { 1035 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 1036 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 1037 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 1038 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 1039 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 1040 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 1041 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 1042 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 1043 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 1044 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 1045 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 1046 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 1047 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 1048 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 1049 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 1050 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 1051 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 1052 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 1053 case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break; 1054 case PAR_EL1: *val = read_sysreg_par(); break; 1055 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 1056 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 1057 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 1058 case ZCR_EL1: *val = read_sysreg_s(SYS_ZCR_EL12); break; 1059 default: return false; 1060 } 1061 1062 return true; 1063 } 1064 __vcpu_write_sys_reg_to_cpu(u64 val,int reg)1065 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 1066 { 1067 /* 1068 * *** VHE ONLY *** 1069 * 1070 * System registers listed in the switch are not restored on every 1071 * entry to the guest but are only restored on vcpu_load. 1072 * 1073 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 1074 * should never be listed below, because the MPIDR should only be set 1075 * once, before running the VCPU, and never changed later. 1076 */ 1077 if (!has_vhe()) 1078 return false; 1079 1080 switch (reg) { 1081 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 1082 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 1083 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 1084 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 1085 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 1086 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 1087 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 1088 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 1089 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 1090 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 1091 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 1092 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 1093 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 1094 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 1095 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 1096 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 1097 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 1098 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 1099 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 1100 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 1101 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 1102 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 1103 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 1104 case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break; 1105 default: return false; 1106 } 1107 1108 return true; 1109 } 1110 1111 struct kvm_vm_stat { 1112 struct kvm_vm_stat_generic generic; 1113 }; 1114 1115 struct kvm_vcpu_stat { 1116 struct kvm_vcpu_stat_generic generic; 1117 u64 hvc_exit_stat; 1118 u64 wfe_exit_stat; 1119 u64 wfi_exit_stat; 1120 u64 mmio_exit_user; 1121 u64 mmio_exit_kernel; 1122 u64 signal_exits; 1123 u64 exits; 1124 }; 1125 1126 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1127 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1128 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1129 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1130 1131 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1132 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1133 1134 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1135 struct kvm_vcpu_events *events); 1136 1137 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1138 struct kvm_vcpu_events *events); 1139 1140 void kvm_arm_halt_guest(struct kvm *kvm); 1141 void kvm_arm_resume_guest(struct kvm *kvm); 1142 1143 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid) 1144 1145 #ifndef __KVM_NVHE_HYPERVISOR__ 1146 #define kvm_call_hyp_nvhe(f, ...) \ 1147 ({ \ 1148 struct arm_smccc_res res; \ 1149 \ 1150 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1151 ##__VA_ARGS__, &res); \ 1152 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1153 \ 1154 res.a1; \ 1155 }) 1156 1157 /* 1158 * The couple of isb() below are there to guarantee the same behaviour 1159 * on VHE as on !VHE, where the eret to EL1 acts as a context 1160 * synchronization event. 1161 */ 1162 #define kvm_call_hyp(f, ...) \ 1163 do { \ 1164 if (has_vhe()) { \ 1165 f(__VA_ARGS__); \ 1166 isb(); \ 1167 } else { \ 1168 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1169 } \ 1170 } while(0) 1171 1172 #define kvm_call_hyp_ret(f, ...) \ 1173 ({ \ 1174 typeof(f(__VA_ARGS__)) ret; \ 1175 \ 1176 if (has_vhe()) { \ 1177 ret = f(__VA_ARGS__); \ 1178 isb(); \ 1179 } else { \ 1180 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1181 } \ 1182 \ 1183 ret; \ 1184 }) 1185 #else /* __KVM_NVHE_HYPERVISOR__ */ 1186 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1187 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1188 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1189 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1190 1191 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1192 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1193 1194 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1195 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1196 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1197 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1198 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1199 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1200 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1201 1202 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1203 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1204 1205 int __init kvm_sys_reg_table_init(void); 1206 struct sys_reg_desc; 1207 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1208 unsigned int idx); 1209 int __init populate_nv_trap_config(void); 1210 1211 bool lock_all_vcpus(struct kvm *kvm); 1212 void unlock_all_vcpus(struct kvm *kvm); 1213 1214 void kvm_calculate_traps(struct kvm_vcpu *vcpu); 1215 1216 /* MMIO helpers */ 1217 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1218 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1219 1220 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1221 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1222 1223 /* 1224 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1225 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1226 * loaded is considered to be "in guest". 1227 */ kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)1228 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1229 { 1230 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1231 } 1232 1233 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1234 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1235 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1236 1237 bool kvm_arm_pvtime_supported(void); 1238 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1239 struct kvm_device_attr *attr); 1240 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1241 struct kvm_device_attr *attr); 1242 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1243 struct kvm_device_attr *attr); 1244 1245 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1246 int __init kvm_arm_vmid_alloc_init(void); 1247 void __init kvm_arm_vmid_alloc_free(void); 1248 bool kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1249 void kvm_arm_vmid_clear_active(void); 1250 kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)1251 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1252 { 1253 vcpu_arch->steal.base = INVALID_GPA; 1254 } 1255 kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)1256 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1257 { 1258 return (vcpu_arch->steal.base != INVALID_GPA); 1259 } 1260 1261 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 1262 1263 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1264 1265 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1266 1267 /* 1268 * How we access per-CPU host data depends on the where we access it from, 1269 * and the mode we're in: 1270 * 1271 * - VHE and nVHE hypervisor bits use their locally defined instance 1272 * 1273 * - the rest of the kernel use either the VHE or nVHE one, depending on 1274 * the mode we're running in. 1275 * 1276 * Unless we're in protected mode, fully deprivileged, and the nVHE 1277 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1278 * In this case, the EL1 code uses the *VHE* data as its private state 1279 * (which makes sense in a way as there shouldn't be any shared state 1280 * between the host and the hypervisor). 1281 * 1282 * Yes, this is all totally trivial. Shoot me now. 1283 */ 1284 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1285 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1286 #else 1287 #define host_data_ptr(f) \ 1288 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1289 &this_cpu_ptr(&kvm_host_data)->f : \ 1290 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1291 #endif 1292 1293 /* Check whether the FP regs are owned by the guest */ guest_owns_fp_regs(void)1294 static inline bool guest_owns_fp_regs(void) 1295 { 1296 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1297 } 1298 1299 /* Check whether the FP regs are owned by the host */ host_owns_fp_regs(void)1300 static inline bool host_owns_fp_regs(void) 1301 { 1302 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1303 } 1304 kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)1305 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1306 { 1307 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1308 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1309 } 1310 kvm_system_needs_idmapped_vectors(void)1311 static inline bool kvm_system_needs_idmapped_vectors(void) 1312 { 1313 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1314 } 1315 kvm_arch_sync_events(struct kvm * kvm)1316 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 1317 1318 void kvm_arm_init_debug(void); 1319 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); 1320 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 1321 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 1322 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 1323 1324 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1325 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1326 1327 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1328 struct kvm_device_attr *attr); 1329 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1330 struct kvm_device_attr *attr); 1331 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1332 struct kvm_device_attr *attr); 1333 1334 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1335 struct kvm_arm_copy_mte_tags *copy_tags); 1336 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1337 struct kvm_arm_counter_offset *offset); 1338 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1339 struct reg_mask_range *range); 1340 1341 /* Guest/host FPSIMD coordination helpers */ 1342 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 1343 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1344 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1345 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1346 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1347 kvm_pmu_counter_deferred(struct perf_event_attr * attr)1348 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1349 { 1350 return (!has_vhe() && attr->exclude_host); 1351 } 1352 1353 /* Flags for host debug state */ 1354 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu); 1355 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); 1356 1357 #ifdef CONFIG_KVM 1358 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); 1359 void kvm_clr_pmu_events(u64 clr); 1360 bool kvm_set_pmuserenr(u64 val); 1361 #else kvm_set_pmu_events(u64 set,struct perf_event_attr * attr)1362 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} kvm_clr_pmu_events(u64 clr)1363 static inline void kvm_clr_pmu_events(u64 clr) {} kvm_set_pmuserenr(u64 val)1364 static inline bool kvm_set_pmuserenr(u64 val) 1365 { 1366 return false; 1367 } 1368 #endif 1369 1370 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1371 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1372 1373 int __init kvm_set_ipa_limit(void); 1374 u32 kvm_get_pa_bits(struct kvm *kvm); 1375 1376 #define __KVM_HAVE_ARCH_VM_ALLOC 1377 struct kvm *kvm_arch_alloc_vm(void); 1378 1379 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1380 1381 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1382 1383 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled) 1384 1385 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1386 1387 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1388 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1389 1390 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1391 1392 #define kvm_has_mte(kvm) \ 1393 (system_supports_mte() && \ 1394 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1395 1396 #define kvm_supports_32bit_el0() \ 1397 (system_supports_32bit_el0() && \ 1398 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1399 1400 #define kvm_vm_has_ran_once(kvm) \ 1401 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1402 __vcpu_has_feature(const struct kvm_arch * ka,int feature)1403 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1404 { 1405 return test_bit(feature, ka->vcpu_features); 1406 } 1407 1408 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1409 1410 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) 1411 1412 int kvm_trng_call(struct kvm_vcpu *vcpu); 1413 #ifdef CONFIG_KVM 1414 extern phys_addr_t hyp_mem_base; 1415 extern phys_addr_t hyp_mem_size; 1416 void __init kvm_hyp_reserve(void); 1417 #else kvm_hyp_reserve(void)1418 static inline void kvm_hyp_reserve(void) { } 1419 #endif 1420 1421 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1422 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1423 __vm_id_reg(struct kvm_arch * ka,u32 reg)1424 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) 1425 { 1426 switch (reg) { 1427 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): 1428 return &ka->id_regs[IDREG_IDX(reg)]; 1429 case SYS_CTR_EL0: 1430 return &ka->ctr_el0; 1431 default: 1432 WARN_ON_ONCE(1); 1433 return NULL; 1434 } 1435 } 1436 1437 #define kvm_read_vm_id_reg(kvm, reg) \ 1438 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; }) 1439 1440 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 1441 1442 #define __expand_field_sign_unsigned(id, fld, val) \ 1443 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1444 1445 #define __expand_field_sign_signed(id, fld, val) \ 1446 ({ \ 1447 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1448 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1449 }) 1450 1451 #define get_idreg_field_unsigned(kvm, id, fld) \ 1452 ({ \ 1453 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \ 1454 FIELD_GET(id##_##fld##_MASK, __val); \ 1455 }) 1456 1457 #define get_idreg_field_signed(kvm, id, fld) \ 1458 ({ \ 1459 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1460 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1461 }) 1462 1463 #define get_idreg_field_enum(kvm, id, fld) \ 1464 get_idreg_field_unsigned(kvm, id, fld) 1465 1466 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \ 1467 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit)) 1468 1469 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \ 1470 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit)) 1471 1472 #define kvm_cmp_feat(kvm, id, fld, op, limit) \ 1473 (id##_##fld##_SIGNED ? \ 1474 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \ 1475 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)) 1476 1477 #define kvm_has_feat(kvm, id, fld, limit) \ 1478 kvm_cmp_feat(kvm, id, fld, >=, limit) 1479 1480 #define kvm_has_feat_enum(kvm, id, fld, val) \ 1481 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val) 1482 1483 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1484 (kvm_cmp_feat(kvm, id, fld, >=, min) && \ 1485 kvm_cmp_feat(kvm, id, fld, <=, max)) 1486 1487 /* Check for a given level of PAuth support */ 1488 #define kvm_has_pauth(k, l) \ 1489 ({ \ 1490 bool pa, pi, pa3; \ 1491 \ 1492 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1493 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1494 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1495 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1496 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1497 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1498 \ 1499 (pa + pi + pa3) == 1; \ 1500 }) 1501 1502 #define kvm_has_fpmr(k) \ 1503 (system_supports_fpmr() && \ 1504 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) 1505 1506 #endif /* __ARM64_KVM_HOST_H__ */ 1507