1 # SPDX-License-Identifier: GPL-2.0-only
2 #
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 #
5 
6 config ARC
7 	def_bool y
8 	select ARC_TIMERS
9 	select ARCH_HAS_CACHE_LINE_SIZE
10 	select ARCH_HAS_DEBUG_VM_PGTABLE
11 	select ARCH_HAS_DMA_PREP_COHERENT
12 	select ARCH_HAS_PTE_SPECIAL
13 	select ARCH_HAS_SETUP_DMA_OPS
14 	select ARCH_HAS_SYNC_DMA_FOR_CPU
15 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 	select ARCH_NEED_CMPXCHG_1_EMU
17 	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
18 	select ARCH_32BIT_OFF_T
19 	select BUILDTIME_TABLE_SORT
20 	select CLONE_BACKWARDS
21 	select COMMON_CLK
22 	select DMA_DIRECT_REMAP
23 	select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
24 	# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
25 	select GENERIC_IRQ_SHOW
26 	select GENERIC_PCI_IOMAP
27 	select GENERIC_PENDING_IRQ if SMP
28 	select GENERIC_SCHED_CLOCK
29 	select GENERIC_SMP_IDLE_THREAD
30 	select GENERIC_IOREMAP
31 	select GENERIC_STRNCPY_FROM_USER if MMU
32 	select GENERIC_STRNLEN_USER if MMU
33 	select HAVE_ARCH_KGDB
34 	select HAVE_ARCH_TRACEHOOK
35 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
36 	select HAVE_DEBUG_STACKOVERFLOW
37 	select HAVE_DEBUG_KMEMLEAK
38 	select HAVE_IOREMAP_PROT
39 	select HAVE_KERNEL_GZIP
40 	select HAVE_KERNEL_LZMA
41 	select HAVE_KPROBES
42 	select HAVE_KRETPROBES
43 	select HAVE_REGS_AND_STACK_ACCESS_API
44 	select HAVE_MOD_ARCH_SPECIFIC
45 	select HAVE_PERF_EVENTS
46 	select HAVE_SYSCALL_TRACEPOINTS
47 	select IRQ_DOMAIN
48 	select LOCK_MM_AND_FIND_VMA
49 	select MODULES_USE_ELF_RELA
50 	select OF
51 	select OF_EARLY_FLATTREE
52 	select PCI_SYSCALL if PCI
53 	select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
54 	select TRACE_IRQFLAGS_SUPPORT
55 	select HAVE_EBPF_JIT if ISA_ARCV2
56 
57 config LOCKDEP_SUPPORT
58 	def_bool y
59 
60 config SCHED_OMIT_FRAME_POINTER
61 	def_bool y
62 
63 config GENERIC_CSUM
64 	def_bool y
65 
66 config ARCH_FLATMEM_ENABLE
67 	def_bool y
68 
69 config MMU
70 	def_bool y
71 
72 config NO_IOPORT_MAP
73 	def_bool y
74 
75 config GENERIC_CALIBRATE_DELAY
76 	def_bool y
77 
78 config GENERIC_HWEIGHT
79 	def_bool y
80 
81 config STACKTRACE_SUPPORT
82 	def_bool y
83 	select STACKTRACE
84 
85 menu "ARC Architecture Configuration"
86 
87 menu "ARC Platform/SoC/Board"
88 
89 source "arch/arc/plat-tb10x/Kconfig"
90 source "arch/arc/plat-axs10x/Kconfig"
91 source "arch/arc/plat-hsdk/Kconfig"
92 
93 endmenu
94 
95 choice
96 	prompt "ARC Instruction Set"
97 	default ISA_ARCV2
98 
99 config ISA_ARCOMPACT
100 	bool "ARCompact ISA"
101 	select CPU_NO_EFFICIENT_FFS
102 	help
103 	  The original ARC ISA of ARC600/700 cores
104 
105 config ISA_ARCV2
106 	bool "ARC ISA v2"
107 	select ARC_TIMERS_64BIT
108 	help
109 	  ISA for the Next Generation ARC-HS cores
110 
111 endchoice
112 
113 menu "ARC CPU Configuration"
114 
115 choice
116 	prompt "ARC Core"
117 	default ARC_CPU_770 if ISA_ARCOMPACT
118 	default ARC_CPU_HS if ISA_ARCV2
119 
120 config ARC_CPU_770
121 	bool "ARC770"
122 	depends on ISA_ARCOMPACT
123 	select ARC_HAS_SWAPE
124 	help
125 	  Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
126 	  This core has a bunch of cool new features:
127 	  -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
128 	           Shared Address Spaces (for sharing TLB entries in MMU)
129 	  -Caches: New Prog Model, Region Flush
130 	  -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
131 
132 config ARC_CPU_HS
133 	bool "ARC-HS"
134 	depends on ISA_ARCV2
135 	help
136 	  Support for ARC HS38x Cores based on ARCv2 ISA
137 	  The notable features are:
138 	    - SMP configurations of up to 4 cores with coherency
139 	    - Optional L2 Cache and IO-Coherency
140 	    - Revised Interrupt Architecture (multiple priorites, reg banks,
141 	        auto stack switch, auto regfile save/restore)
142 	    - MMUv4 (PIPT dcache, Huge Pages)
143 	    - Instructions for
144 		* 64bit load/store: LDD, STD
145 		* Hardware assisted divide/remainder: DIV, REM
146 		* Function prologue/epilogue: ENTER_S, LEAVE_S
147 		* IRQ enable/disable: CLRI, SETI
148 		* pop count: FFS, FLS
149 		* SETcc, BMSKN, XBFU...
150 
151 endchoice
152 
153 config ARC_TUNE_MCPU
154 	string "Override default -mcpu compiler flag"
155 	default ""
156 	help
157 	  Override default -mcpu=xxx compiler flag (which is set depending on
158 	  the ISA version) with the specified value.
159 	  NOTE: If specified flag isn't supported by current compiler the
160 	  ISA default value will be used as a fallback.
161 
162 config CPU_BIG_ENDIAN
163 	bool "Enable Big Endian Mode"
164 	help
165 	  Build kernel for Big Endian Mode of ARC CPU
166 
167 config SMP
168 	bool "Symmetric Multi-Processing"
169 	select ARC_MCIP if ISA_ARCV2
170 	help
171 	  This enables support for systems with more than one CPU.
172 
173 if SMP
174 
175 config NR_CPUS
176 	int "Maximum number of CPUs (2-4096)"
177 	range 2 4096
178 	default "4"
179 
180 config ARC_SMP_HALT_ON_RESET
181 	bool "Enable Halt-on-reset boot mode"
182 	help
183 	  In SMP configuration cores can be configured as Halt-on-reset
184 	  or they could all start at same time. For Halt-on-reset, non
185 	  masters are parked until Master kicks them so they can start off
186 	  at designated entry point. For other case, all jump to common
187 	  entry point and spin wait for Master's signal.
188 
189 endif #SMP
190 
191 config ARC_MCIP
192 	bool "ARConnect Multicore IP (MCIP) Support "
193 	depends on ISA_ARCV2
194 	default y if SMP
195 	help
196 	  This IP block enables SMP in ARC-HS38 cores.
197 	  It provides for cross-core interrupts, multi-core debug
198 	  hardware semaphores, shared memory,....
199 
200 menuconfig ARC_CACHE
201 	bool "Enable Cache Support"
202 	default y
203 
204 if ARC_CACHE
205 
206 config ARC_CACHE_LINE_SHIFT
207 	int "Cache Line Length (as power of 2)"
208 	range 5 7
209 	default "6"
210 	help
211 	  Starting with ARC700 4.9, Cache line length is configurable,
212 	  This option specifies "N", with Line-len = 2 power N
213 	  So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
214 	  Linux only supports same line lengths for I and D caches.
215 
216 config ARC_HAS_ICACHE
217 	bool "Use Instruction Cache"
218 	default y
219 
220 config ARC_HAS_DCACHE
221 	bool "Use Data Cache"
222 	default y
223 
224 config ARC_CACHE_PAGES
225 	bool "Per Page Cache Control"
226 	default y
227 	depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
228 	help
229 	  This can be used to over-ride the global I/D Cache Enable on a
230 	  per-page basis (but only for pages accessed via MMU such as
231 	  Kernel Virtual address or User Virtual Address)
232 	  TLB entries have a per-page Cache Enable Bit.
233 	  Note that Global I/D ENABLE + Per Page DISABLE works but corollary
234 	  Global DISABLE + Per Page ENABLE won't work
235 
236 endif #ARC_CACHE
237 
238 config ARC_HAS_ICCM
239 	bool "Use ICCM"
240 	help
241 	  Single Cycle RAMS to store Fast Path Code
242 
243 config ARC_ICCM_SZ
244 	int "ICCM Size in KB"
245 	default "64"
246 	depends on ARC_HAS_ICCM
247 
248 config ARC_HAS_DCCM
249 	bool "Use DCCM"
250 	help
251 	  Single Cycle RAMS to store Fast Path Data
252 
253 config ARC_DCCM_SZ
254 	int "DCCM Size in KB"
255 	default "64"
256 	depends on ARC_HAS_DCCM
257 
258 config ARC_DCCM_BASE
259 	hex "DCCM map address"
260 	default "0xA0000000"
261 	depends on ARC_HAS_DCCM
262 
263 choice
264 	prompt "MMU Version"
265 	default ARC_MMU_V3 if ISA_ARCOMPACT
266 	default ARC_MMU_V4 if ISA_ARCV2
267 
268 config ARC_MMU_V3
269 	bool "MMU v3"
270 	depends on ISA_ARCOMPACT
271 	help
272 	  Introduced with ARC700 4.10: New Features
273 	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
274 	  Shared Address Spaces (SASID)
275 
276 config ARC_MMU_V4
277 	bool "MMU v4"
278 	depends on ISA_ARCV2
279 
280 endchoice
281 
282 
283 choice
284 	prompt "MMU Page Size"
285 	default ARC_PAGE_SIZE_8K
286 
287 config ARC_PAGE_SIZE_8K
288 	bool "8KB"
289 	select HAVE_PAGE_SIZE_8KB
290 	help
291 	  Choose between 8k vs 16k
292 
293 config ARC_PAGE_SIZE_16K
294 	select HAVE_PAGE_SIZE_16KB
295 	bool "16KB"
296 
297 config ARC_PAGE_SIZE_4K
298 	bool "4KB"
299 	select HAVE_PAGE_SIZE_4KB
300 	depends on ARC_MMU_V3 || ARC_MMU_V4
301 
302 endchoice
303 
304 choice
305 	prompt "MMU Super Page Size"
306 	depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
307 	default ARC_HUGEPAGE_2M
308 
309 config ARC_HUGEPAGE_2M
310 	bool "2MB"
311 
312 config ARC_HUGEPAGE_16M
313 	bool "16MB"
314 
315 endchoice
316 
317 config PGTABLE_LEVELS
318 	int "Number of Page table levels"
319 	default 2
320 
321 config ARC_COMPACT_IRQ_LEVELS
322 	depends on ISA_ARCOMPACT
323 	bool "Setup Timer IRQ as high Priority"
324 	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
325 	depends on !SMP
326 
327 config ARC_FPU_SAVE_RESTORE
328 	bool "Enable FPU state persistence across context switch"
329 	help
330 	  ARCompact FPU has internal registers to assist with Double precision
331 	  Floating Point operations. There are control and stauts registers
332 	  for floating point exceptions and rounding modes. These are
333 	  preserved across task context switch when enabled.
334 
335 config ARC_CANT_LLSC
336 	def_bool n
337 
338 config ARC_HAS_LLSC
339 	bool "Insn: LLOCK/SCOND (efficient atomic ops)"
340 	default y
341 	depends on !ARC_CANT_LLSC
342 
343 config ARC_HAS_SWAPE
344 	bool "Insn: SWAPE (endian-swap)"
345 	default y
346 
347 if ISA_ARCV2
348 
349 config ARC_USE_UNALIGNED_MEM_ACCESS
350 	bool "Enable unaligned access in HW"
351 	default y
352 	select HAVE_EFFICIENT_UNALIGNED_ACCESS
353 	help
354 	  The ARC HS architecture supports unaligned memory access
355 	  which is disabled by default. Enable unaligned access in
356 	  hardware and use software to use it
357 
358 config ARC_HAS_LL64
359 	bool "Insn: 64bit LDD/STD"
360 	help
361 	  Enable gcc to generate 64-bit load/store instructions
362 	  ISA mandates even/odd registers to allow encoding of two
363 	  dest operands with 2 possible source operands.
364 	default y
365 
366 config ARC_HAS_DIV_REM
367 	bool "Insn: div, divu, rem, remu"
368 	default y
369 
370 config ARC_HAS_ACCL_REGS
371 	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
372 	default y
373 	help
374 	  Depending on the configuration, CPU can contain accumulator reg-pair
375 	  (also referred to as r58:r59). These can also be used by gcc as GPR so
376 	  kernel needs to save/restore per process
377 
378 config ARC_DSP_HANDLED
379 	def_bool n
380 
381 config ARC_DSP_SAVE_RESTORE_REGS
382 	def_bool n
383 
384 choice
385 	prompt "DSP support"
386 	default ARC_DSP_NONE
387 	help
388 	  Depending on the configuration, CPU can contain DSP registers
389 	  (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
390 	  Below are options describing how to handle these registers in
391 	  interrupt entry / exit and in context switch.
392 
393 config ARC_DSP_NONE
394 	bool "No DSP extension presence in HW"
395 	help
396 	  No DSP extension presence in HW
397 
398 config ARC_DSP_KERNEL
399 	bool "DSP extension in HW, no support for userspace"
400 	select ARC_HAS_ACCL_REGS
401 	select ARC_DSP_HANDLED
402 	help
403 	  DSP extension presence in HW, no support for DSP-enabled userspace
404 	  applications. We don't save / restore DSP registers and only do
405 	  some minimal preparations so userspace won't be able to break kernel
406 
407 config ARC_DSP_USERSPACE
408 	bool "Support DSP for userspace apps"
409 	select ARC_HAS_ACCL_REGS
410 	select ARC_DSP_HANDLED
411 	select ARC_DSP_SAVE_RESTORE_REGS
412 	help
413 	  DSP extension presence in HW, support save / restore DSP registers to
414 	  run DSP-enabled userspace applications
415 
416 config ARC_DSP_AGU_USERSPACE
417 	bool "Support DSP with AGU for userspace apps"
418 	select ARC_HAS_ACCL_REGS
419 	select ARC_DSP_HANDLED
420 	select ARC_DSP_SAVE_RESTORE_REGS
421 	help
422 	  DSP and AGU extensions presence in HW, support save / restore DSP
423 	  and AGU registers to run DSP-enabled userspace applications
424 endchoice
425 
426 config ARC_IRQ_NO_AUTOSAVE
427 	bool "Disable hardware autosave regfile on interrupts"
428 	default n
429 	help
430 	  On HS cores, taken interrupt auto saves the regfile on stack.
431 	  This is programmable and can be optionally disabled in which case
432 	  software INTERRUPT_PROLOGUE/EPILGUE do the needed work
433 
434 config ARC_LPB_DISABLE
435 	bool "Disable loop buffer (LPB)"
436 	help
437 	  On HS cores, loop buffer (LPB) is programmable in runtime and can
438 	  be optionally disabled.
439 
440 endif # ISA_ARCV2
441 
442 endmenu   # "ARC CPU Configuration"
443 
444 config LINUX_LINK_BASE
445 	hex "Kernel link address"
446 	default "0x80000000"
447 	help
448 	  ARC700 divides the 32 bit phy address space into two equal halves
449 	  -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
450 	  -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
451 	  Typically Linux kernel is linked at the start of untransalted addr,
452 	  hence the default value of 0x8zs.
453 	  However some customers have peripherals mapped at this addr, so
454 	  Linux needs to be scooted a bit.
455 	  If you don't know what the above means, leave this setting alone.
456 	  This needs to match memory start address specified in Device Tree
457 
458 config LINUX_RAM_BASE
459 	hex "RAM base address"
460 	default LINUX_LINK_BASE
461 	help
462 	  By default Linux is linked at base of RAM. However in some special
463 	  cases (such as HSDK), Linux can't be linked at start of DDR, hence
464 	  this option.
465 
466 config HIGHMEM
467 	bool "High Memory Support"
468 	select HAVE_ARCH_PFN_VALID
469 	select KMAP_LOCAL
470 	help
471 	  With ARC 2G:2G address split, only upper 2G is directly addressable by
472 	  kernel. Enable this to potentially allow access to rest of 2G and PAE
473 	  in future
474 
475 config ARC_HAS_PAE40
476 	bool "Support for the 40-bit Physical Address Extension"
477 	depends on ISA_ARCV2
478 	select HIGHMEM
479 	select PHYS_ADDR_T_64BIT
480 	help
481 	  Enable access to physical memory beyond 4G, only supported on
482 	  ARC cores with 40 bit Physical Addressing support
483 
484 config ARC_KVADDR_SIZE
485 	int "Kernel Virtual Address Space size (MB)"
486 	range 0 512
487 	default "256"
488 	help
489 	  The kernel address space is carved out of 256MB of translated address
490 	  space for catering to vmalloc, modules, pkmap, fixmap. This however may
491 	  not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
492 	  this to be stretched to 512 MB (by extending into the reserved
493 	  kernel-user gutter)
494 
495 config ARC_CURR_IN_REG
496 	bool "cache current task pointer in gp"
497 	default y
498 	help
499 	  This reserves gp register to point to Current Task in
500 	  kernel mode eliding memory access for each access
501 
502 
503 config ARC_EMUL_UNALIGNED
504 	bool "Emulate unaligned memory access (userspace only)"
505 	select SYSCTL_ARCH_UNALIGN_NO_WARN
506 	select SYSCTL_ARCH_UNALIGN_ALLOW
507 	depends on ISA_ARCOMPACT
508 	help
509 	  This enables misaligned 16 & 32 bit memory access from user space.
510 	  Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
511 	  potential bugs in code
512 
513 config HZ
514 	int "Timer Frequency"
515 	default 100
516 
517 config ARC_METAWARE_HLINK
518 	bool "Support for Metaware debugger assisted Host access"
519 	help
520 	  This options allows a Linux userland apps to directly access
521 	  host file system (open/creat/read/write etc) with help from
522 	  Metaware Debugger. This can come in handy for Linux-host communication
523 	  when there is no real usable peripheral such as EMAC.
524 
525 menuconfig ARC_DBG
526 	bool "ARC debugging"
527 	default y
528 
529 if ARC_DBG
530 
531 config ARC_DW2_UNWIND
532 	bool "Enable DWARF specific kernel stack unwind"
533 	default y
534 	select KALLSYMS
535 	help
536 	  Compiles the kernel with DWARF unwind information and can be used
537 	  to get stack backtraces.
538 
539 	  If you say Y here the resulting kernel image will be slightly larger
540 	  but not slower, and it will give very useful debugging information.
541 	  If you don't debug the kernel, you can say N, but we may not be able
542 	  to solve problems without frame unwind information
543 
544 config ARC_DBG_JUMP_LABEL
545 	bool "Paranoid checks in Static Keys (jump labels) code"
546 	depends on JUMP_LABEL
547 	default y if STATIC_KEYS_SELFTEST
548 	help
549 	  Enable paranoid checks and self-test of both ARC-specific and generic
550 	  part of static keys (jump labels) related code.
551 endif
552 
553 config ARC_BUILTIN_DTB_NAME
554 	string "Built in DTB"
555 	help
556 	  Set the name of the DTB to embed in the vmlinux binary
557 	  Leaving it blank selects the "nsim_700" dtb.
558 
559 endmenu	 # "ARC Architecture Configuration"
560 
561 config ARCH_FORCE_MAX_ORDER
562 	int "Maximum zone order"
563 	default "11" if ARC_HUGEPAGE_16M
564 	default "10"
565 
566 source "kernel/power/Kconfig"
567