| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn401/ |
| D | dcn401_fpu.c | 30 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_secon… in dcn401_build_wm_range_table_fpu()
32 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_… in dcn401_build_wm_range_table_fpu()
38 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn401_build_wm_range_table_fpu()
39 clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn401_build_wm_range_table_fpu()
40 …clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_laten… in dcn401_build_wm_range_table_fpu()
41 clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
42 …clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus… in dcn401_build_wm_range_table_fpu()
43 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn401_build_wm_range_table_fpu()
44 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
45 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn401_build_wm_range_table_fpu()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.h | 33 extern struct wm_table ddr4_wm_table_gs;
34 extern struct wm_table lpddr4_wm_table_gs;
35 extern struct wm_table lpddr4_wm_table_with_disabled_ppt;
36 extern struct wm_table ddr4_wm_table_rn;
37 extern struct wm_table ddr4_1R_wm_table_rn;
38 extern struct wm_table lpddr4_wm_table_rn;
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| D | rn_clk_mgr.c | 462 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()
466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()
679 bw_params->wm_table.entries[i].wm_inst = i; in rn_clk_mgr_helper_populate_bw_params()
682 bw_params->wm_table.entries[i].valid = false; in rn_clk_mgr_helper_populate_bw_params()
686 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in rn_clk_mgr_helper_populate_bw_params()
687 bw_params->wm_table.entries[i].valid = true; in rn_clk_mgr_helper_populate_bw_params()
745 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; in rn_clk_mgr_construct()
748 rn_bw_params.wm_table = lpddr4_wm_table_gs; in rn_clk_mgr_construct()
750 rn_bw_params.wm_table = lpddr4_wm_table_rn; in rn_clk_mgr_construct()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_fpu_update_soc_for_wm_a()
373 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
374 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_update_soc_for_wm_a()
375 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_fpu_update_soc_for_wm_a()
417 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
436 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_fpu_calculate_wm_and_dlg()
441 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
442 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_calculate_wm_and_dlg()
443 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn30_fpu_calculate_wm_and_dlg()
483 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_fpu_calculate_wm_and_dlg()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.c | 265 static struct wm_table ddr4_wm_table = {
302 static struct wm_table lpddr5_wm_table = {
351 if (!bw_params->wm_table.entries[i].valid) in dcn316_build_watermark_ranges()
354 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn316_build_watermark_ranges()
355 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn316_build_watermark_ranges()
548 bw_params->wm_table.entries[i].wm_inst = i; in dcn316_clk_mgr_helper_populate_bw_params()
551 bw_params->wm_table.entries[i].valid = false; in dcn316_clk_mgr_helper_populate_bw_params()
555 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn316_clk_mgr_helper_populate_bw_params()
556 bw_params->wm_table.entries[i].valid = true; in dcn316_clk_mgr_helper_populate_bw_params()
635 dcn316_bw_params.wm_table = lpddr5_wm_table; in dcn316_clk_mgr_construct()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.h | 32 extern struct wm_table ddr4_wm_table;
33 extern struct wm_table lpddr5_wm_table;
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| D | vg_clk_mgr.c | 394 if (!bw_params->wm_table.entries[i].valid) in vg_build_watermark_ranges()
397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in vg_build_watermark_ranges()
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in vg_build_watermark_ranges()
604 bw_params->wm_table.entries[i].wm_inst = i; in vg_clk_mgr_helper_populate_bw_params()
607 bw_params->wm_table.entries[i].valid = false; in vg_clk_mgr_helper_populate_bw_params()
611 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in vg_clk_mgr_helper_populate_bw_params()
612 bw_params->wm_table.entries[i].valid = true; in vg_clk_mgr_helper_populate_bw_params()
721 vg_bw_params.wm_table = lpddr5_wm_table; in vg_clk_mgr_construct()
723 vg_bw_params.wm_table = ddr4_wm_table; in vg_clk_mgr_construct()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 203 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_… in dcn32_build_wm_range_table_fpu()
205 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa… in dcn32_build_wm_range_table_fpu()
211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn32_build_wm_range_table_fpu()
212 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()
213 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_… in dcn32_build_wm_range_table_fpu()
214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
215 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn32_build_wm_range_table_fpu()
216 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn32_build_wm_range_table_fpu()
217 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
218 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 343 static struct wm_table ddr5_wm_table = {
380 static struct wm_table lpddr5_wm_table = {
429 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
620 bw_params->wm_table.entries[i].wm_inst = i; in dcn31_clk_mgr_helper_populate_bw_params()
623 bw_params->wm_table.entries[i].valid = false; in dcn31_clk_mgr_helper_populate_bw_params()
627 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn31_clk_mgr_helper_populate_bw_params()
628 bw_params->wm_table.entries[i].valid = true; in dcn31_clk_mgr_helper_populate_bw_params()
728 dcn31_bw_params.wm_table = lpddr5_wm_table; in dcn31_clk_mgr_construct()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_clk_mgr.c | 303 static struct wm_table ddr5_wm_table = {
340 static struct wm_table lpddr5_wm_table = {
389 if (!bw_params->wm_table.entries[i].valid) in dcn315_build_watermark_ranges()
392 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn315_build_watermark_ranges()
393 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn315_build_watermark_ranges()
572 bw_params->wm_table.entries[i].wm_inst = i; in dcn315_clk_mgr_helper_populate_bw_params()
575 bw_params->wm_table.entries[i].valid = false; in dcn315_clk_mgr_helper_populate_bw_params()
579 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn315_clk_mgr_helper_populate_bw_params()
580 bw_params->wm_table.entries[i].valid = true; in dcn315_clk_mgr_helper_populate_bw_params()
655 dcn315_bw_params.wm_table = lpddr5_wm_table; in dcn315_clk_mgr_construct()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 218 struct wm_table ddr4_wm_table = {
255 struct wm_table lpddr5_wm_table = {
429 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_fpu_calculate_wm_and_dlg()
437 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn301_fpu_calculate_wm_and_dlg()
442 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn301_fpu_calculate_wm_and_dlg()
448 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_fpu_calculate_wm_and_dlg()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 403 static struct wm_table ddr5_wm_table = {
440 static struct wm_table lpddr5_wm_table = {
494 if (!bw_params->wm_table.entries[i].valid) in dcn314_build_watermark_ranges()
497 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn314_build_watermark_ranges()
498 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn314_build_watermark_ranges()
742 bw_params->wm_table.entries[i].wm_inst = i; in dcn314_clk_mgr_helper_populate_bw_params()
745 bw_params->wm_table.entries[i].valid = false; in dcn314_clk_mgr_helper_populate_bw_params()
749 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn314_clk_mgr_helper_populate_bw_params()
750 bw_params->wm_table.entries[i].valid = true; in dcn314_clk_mgr_helper_populate_bw_params()
839 dcn314_bw_params.wm_table = lpddr5_wm_table; in dcn314_clk_mgr_construct()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 340 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn3_notify_wm_ranges()
341 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
342 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
343 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
344 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
346 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries… in dcn3_notify_wm_ranges()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 236 struct wm_table { struct
256 struct wm_table wm_table; argument
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| D | dcn401_clk_mgr.c | 181 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn401_build_wm_range_table()
182 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn401_build_wm_range_table()
183 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn401_build_wm_range_table()
184 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn401_build_wm_range_table()
185 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn401_build_wm_range_table()
186 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn401_build_wm_range_table()
189 clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false; in dcn401_build_wm_range_table()
194 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true; in dcn401_build_wm_range_table()
195 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; in dcn401_build_wm_range_table()
196 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn401_build_wm_range_table()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| D | dcn35_clk_mgr.c | 542 static struct wm_table ddr5_wm_table = {
579 static struct wm_table lpddr5_wm_table = {
650 if (!bw_params->wm_table.entries[i].valid) in dcn35_build_watermark_ranges()
653 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn35_build_watermark_ranges()
654 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn35_build_watermark_ranges()
940 bw_params->wm_table.entries[i].wm_inst = i; in dcn35_clk_mgr_helper_populate_bw_params()
943 bw_params->wm_table.entries[i].valid = false; in dcn35_clk_mgr_helper_populate_bw_params()
947 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn35_clk_mgr_helper_populate_bw_params()
948 bw_params->wm_table.entries[i].valid = true; in dcn35_clk_mgr_helper_populate_bw_params()
1135 dcn35_bw_params.wm_table = lpddr5_wm_table; in dcn35_clk_mgr_construct()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 768 struct wm_table ddr4_wm_table_gs = {
805 struct wm_table lpddr4_wm_table_gs = {
842 struct wm_table lpddr4_wm_table_with_disabled_ppt = {
879 struct wm_table ddr4_wm_table_rn = {
916 struct wm_table ddr4_1R_wm_table_rn = {
953 struct wm_table lpddr4_wm_table_rn = {
2183 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = in patch_bounding_box()
2190 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = in patch_bounding_box()
2201 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = in patch_bounding_box()
2296 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.c | 984 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn32_notify_wm_ranges()
986 …table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_bre… in dcn32_notify_wm_ranges()
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 2563 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task() local
2568 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega12_display_configuration_changed_task()
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| D | vega20_hwmgr.c | 3656 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega20_display_configuration_changed_task() local
3661 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega20_display_configuration_changed_task()
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| D | vega10_hwmgr.c | 4971 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega10_display_configuration_changed_task() local
4976 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); in vega10_display_configuration_changed_task()
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