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Searched refs:vsync_source (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c123 if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 && in dpu_hw_setup_wd_timer()
124 cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) { in dpu_hw_setup_wd_timer()
125 switch (cfg->vsync_source) { in dpu_hw_setup_wd_timer()
188 reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx]; in dpu_hw_setup_vsync_sel()
Ddpu_hw_top.h67 enum dpu_vsync_source vsync_source; member
Ddpu_encoder.h36 enum dpu_vsync_source vsync_source; member
Ddpu_hw_intf.h111 void (*vsync_sel)(struct dpu_hw_intf *intf, enum dpu_vsync_source vsync_source);
Ddpu_hw_intf.c480 enum dpu_vsync_source vsync_source) in dpu_hw_intf_vsync_sel() argument
489 DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf)); in dpu_hw_intf_vsync_sel()
Ddpu_kms.c530 info->vsync_source = DPU_VSYNC_SOURCE_GPIO_0; in dpu_kms_dsi_set_te_source()
538 info->vsync_source = i; in dpu_kms_dsi_set_te_source()
Ddpu_encoder.c779 vsync_cfg.vsync_source = disp_info->vsync_source; in _dpu_encoder_update_vsync_source()
788 vsync_cfg.vsync_source); in _dpu_encoder_update_vsync_source()