Home
last modified time | relevance | path

Searched refs:sg_pci (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/arch/alpha/kernel/
Dcore_titan.c322 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, in titan_init_one_pachip_port()
324 hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */ in titan_init_one_pachip_port()
334 port->wsba[2].csr = hose->sg_pci->dma_base | 3; in titan_init_one_pachip_port()
335 port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000; in titan_init_one_pachip_port()
336 port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes); in titan_init_one_pachip_port()
497 if (hose->sg_pci && in titan_ioremap()
498 baddr >= (unsigned long)hose->sg_pci->dma_base && in titan_ioremap()
499 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size){ in titan_ioremap()
504 baddr -= hose->sg_pci->dma_base; in titan_ioremap()
505 last -= hose->sg_pci->dma_base; in titan_ioremap()
[all …]
Dcore_marvel.c307 hose->sg_pci = iommu_arena_new_node(0, hose, 0xc0000000, 0x40000000, 0); in io7_init_hose()
308 hose->sg_pci->align_entry = 8; /* cache line boundary */ in io7_init_hose()
310 hose->sg_pci->dma_base | wbase_m_ena | wbase_m_sg; in io7_init_hose()
311 csrs->POx_WMASK[2].csr = (hose->sg_pci->size - 1) & wbase_m_addr; in io7_init_hose()
312 csrs->POx_TBASE[2].csr = virt_to_phys(hose->sg_pci->ptes); in io7_init_hose()
726 if (hose->sg_pci && in marvel_ioremap()
727 baddr >= (unsigned long)hose->sg_pci->dma_base && in marvel_ioremap()
728 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size) { in marvel_ioremap()
733 baddr -= hose->sg_pci->dma_base; in marvel_ioremap()
734 last -= hose->sg_pci->dma_base; in marvel_ioremap()
[all …]
Dcore_tsunami.c327 hose->sg_pci = iommu_arena_new(hose, 0x40000000, in tsunami_init_one_pchip()
330 hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */ in tsunami_init_one_pchip()
339 pchip->wsba[1].csr = hose->sg_pci->dma_base | 3; in tsunami_init_one_pchip()
340 pchip->wsm[1].csr = (hose->sg_pci->size - 1) & 0xfff00000; in tsunami_init_one_pchip()
341 pchip->tba[1].csr = virt_to_phys(hose->sg_pci->ptes); in tsunami_init_one_pchip()
Dcore_mcpcia.c369 hose->sg_pci = iommu_arena_new(hose, 0x40000000, in mcpcia_startup_hose()
380 *(vuip)MCPCIA_W1_BASE(mid) = hose->sg_pci->dma_base | 3; in mcpcia_startup_hose()
381 *(vuip)MCPCIA_W1_MASK(mid) = (hose->sg_pci->size - 1) & 0xfff00000; in mcpcia_startup_hose()
382 *(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8; in mcpcia_startup_hose()
Dpci.c100 struct pci_iommu_arena *pci = hose->sg_pci; in quirk_cypress()
335 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0; in common_init_pci()
Dcore_wildfire.c116 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x08000000, in wildfire_init_hose()
133 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
134 pci->pci_window[3].wmask.csr = (hose->sg_pci->size - 1) & 0xfff00000; in wildfire_init_hose()
135 pci->pci_window[3].tbase.csr = virt_to_phys(hose->sg_pci->ptes); in wildfire_init_hose()
Dpci_iommu.c277 arena = hose->sg_pci; in pci_map_single_1()
379 arena = hose->sg_pci; in alpha_pci_unmap_page()
669 arena = hose->sg_pci; in alpha_pci_map_sg()
734 arena = hose->sg_pci; in alpha_pci_unmap_sg()
813 arena = hose->sg_pci; in alpha_pci_supported()
Dcore_polaris.c173 hose->sg_isa = hose->sg_pci = NULL; in polaris_init_arch()
Dcore_irongate.c292 hose->sg_isa = hose->sg_pci = NULL; in irongate_init_arch()
Dcore_t2.c355 hose->sg_pci = NULL; in t2_sg_map_window2()
Dsys_dp264.c535 hose_head->sg_pci->align_entry = 4; in webbrick_init_arch()
Dcore_cia.c729 hose->sg_pci = NULL; in do_init_arch()
/linux-6.12.1/arch/alpha/include/asm/
Dpci.h43 struct pci_iommu_arena *sg_pci; member