Searched refs:regUVD_VCPU_CACHE_SIZE2 (Results 1 – 9 of 9) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v4_0_3.c | 427 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, in vcn_v4_0_3_mc_resume()
535 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
998 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_3_start_sriov()
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| D | vcn_v4_0.c | 462 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_mc_resume()
561 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1393 regUVD_VCPU_CACHE_SIZE2), in vcn_v4_0_start_sriov()
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| D | vcn_v5_0_0.c | 374 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v5_0_0_mc_resume()
474 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
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| D | vcn_v4_0_5.c | 410 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_5_mc_resume()
515 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_2_6_0_offset.h | 40 #define regUVD_VCPU_CACHE_SIZE2 … macro
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| D | vcn_5_0_0_offset.h | 378 #define regUVD_VCPU_CACHE_SIZE2 … macro
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| D | vcn_4_0_5_offset.h | 371 #define regUVD_VCPU_CACHE_SIZE2 … macro
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| D | vcn_4_0_0_offset.h | 388 #define regUVD_VCPU_CACHE_SIZE2 … macro
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| D | vcn_4_0_3_offset.h | 390 #define regUVD_VCPU_CACHE_SIZE2 … macro
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