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Searched refs:regSDMA0_UTCL1_WR_XNACK0_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/sdma/
Dsdma_4_4_0_offset.h124 #define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h123 #define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX … macro
Dgc_12_0_0_offset.h115 #define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX … macro
Dgc_11_0_0_offset.h121 #define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX … macro
Dgc_11_0_3_offset.h121 #define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX … macro