Home
last modified time | relevance | path

Searched refs:regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h344 #define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX … macro
Dgc_12_0_0_offset.h337 #define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX … macro
Dgc_11_0_0_offset.h339 #define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX … macro
Dgc_11_0_3_offset.h345 #define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX … macro