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Searched refs:regCP_HQD_IQ_TIMER (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h735 #define regCP_HQD_IQ_TIMER … macro
Dgc_9_4_3_offset.h3324 #define regCP_HQD_IQ_TIMER … macro
Dgc_11_5_0_offset.h3615 #define regCP_HQD_IQ_TIMER … macro
Dgc_12_0_0_offset.h3884 #define regCP_HQD_IQ_TIMER … macro
Dgc_11_0_0_offset.h4642 #define regCP_HQD_IQ_TIMER … macro
Dgc_11_0_3_offset.h4866 #define regCP_HQD_IQ_TIMER … macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_3.c2067 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); in gfx_v9_4_3_xcc_q_fini_register()