Home
last modified time | relevance | path

Searched refs:refcyc_per_meta_chunk_vblank_l (Results 1 – 25 of 25) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddisplay_rq_dlg_calc_32.c261 double refcyc_per_meta_chunk_vblank_l; in dml32_rq_dlg_get_dlg_reg() local
495 refcyc_per_meta_chunk_vblank_l = get_refcyc_per_meta_chunk_vblank_l_in_us(mode_lib, e2e_pipe_param, in dml32_rq_dlg_get_dlg_reg()
516 dlg_regs->refcyc_per_meta_chunk_vblank_l = refcyc_per_meta_chunk_vblank_l; in dml32_rq_dlg_get_dlg_reg()
601 ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml32_rq_dlg_get_dlg_reg()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
Ddml_display_rq_dlg_calc.c260 dml_float_t refcyc_per_meta_chunk_vblank_l; in dml_rq_dlg_get_dlg_reg() local
461 …refcyc_per_meta_chunk_vblank_l = dml_get_refcyc_per_meta_chunk_vblank_l_in_us(mode_lib, pipe_idx) … in dml_rq_dlg_get_dlg_reg()
478 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (dml_uint_t)(refcyc_per_meta_chunk_vblank_l); in dml_rq_dlg_get_dlg_reg()
561 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (dml_uint_t)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_reg()
Ddml2_translation_helper.c1451 out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; in dml2_update_pipe_ctx_dchub_regs()
Ddisplay_mode_util.c269 …dml_print("DML: refcyc_per_meta_chunk_vblank_l = 0x%x\n", dlg_regs->refcyc_per_meta_chunk_vblank_l… in dml_print_dlg_regs_st()
Ddisplay_mode_core_structs.h1889 dml_uint_t refcyc_per_meta_chunk_vblank_l; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
Ddcn21_hubp.c424 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp21_validate_dml_output()
470 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) in hubp21_validate_dml_output()
472 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp21_validate_dml_output()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
Ddcn20_hubp.c269 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp2_setup_interdependent()
1174 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp2_read_state_common()
1517 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp2_validate_dml_output()
1563 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) in hubp2_validate_dml_output()
1565 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp2_validate_dml_output()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
Ddml_top_dchub_registers.h51 uint32_t refcyc_per_meta_chunk_vblank_l; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c1490 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml_rq_dlg_get_dlg_params()
1494 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 0; in dml_rq_dlg_get_dlg_params()
1495 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1498 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assig… in dml_rq_dlg_get_dlg_params()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_rq_dlg_helpers.c245 dlg_regs->refcyc_per_meta_chunk_vblank_l); in print__dlg_regs_st()
Ddisplay_mode_structs.h639 unsigned int refcyc_per_meta_chunk_vblank_l; member
Ddml1_display_rq_dlg_calc.c1540 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml1_rq_dlg_get_dlg_params()
1543 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); in dml1_rq_dlg_get_dlg_params()
1546 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assign… in dml1_rq_dlg_get_dlg_params()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20.c1406 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml20_rq_dlg_get_dlg_params()
1409 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); in dml20_rq_dlg_get_dlg_params()
1412 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assig… in dml20_rq_dlg_get_dlg_params()
Ddisplay_rq_dlg_calc_20v2.c1407 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml20v2_rq_dlg_get_dlg_params()
1410 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); in dml20v2_rq_dlg_get_dlg_params()
1413 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assig… in dml20v2_rq_dlg_get_dlg_params()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_rq_dlg_calc_31.c1430 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) ht… in dml_rq_dlg_get_dlg_params()
1431 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1433 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // … in dml_rq_dlg_get_dlg_params()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c1582 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml_rq_dlg_get_dlg_params()
1585 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1588 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assig… in dml_rq_dlg_get_dlg_params()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
Ddcn401_hubp.c333 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp401_setup_interdependent()
827 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp401_read_state()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/
Ddisplay_rq_dlg_calc_314.c1518 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) ht… in dml_rq_dlg_get_dlg_params()
1519 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1521 …disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // … in dml_rq_dlg_get_dlg_params()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
Ddcn10_hubp.c708 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp1_setup_interdependent()
939 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp1_read_state_common()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer_debug.c266 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_get_dlg_states()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
Ddcn20_hwseq.c1607 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || in dcn20_detect_pipe_changes()
1625 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; in dcn20_detect_pipe_changes()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
Ddml2_core_shared_types.h1450 double refcyc_per_meta_chunk_vblank_l; member
Ddml2_core_shared.c11842 …l->refcyc_per_meta_chunk_vblank_l = mode_lib->mp.TimePerMetaChunkVBlank[mode_lib->mp.pipe_plane[pi… in rq_dlg_get_dlg_reg()
11851 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int)(l->refcyc_per_meta_chunk_vblank_l); in rq_dlg_get_dlg_reg()
Ddml2_core_dcn4_calcs.c12149 …l->refcyc_per_meta_chunk_vblank_l = mode_lib->mp.TimePerMetaChunkVBlank[mode_lib->mp.pipe_plane[pi… in rq_dlg_get_dlg_reg()
12158 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int)(l->refcyc_per_meta_chunk_vblank_l); in rq_dlg_get_dlg_reg()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
Ddcn10_hwseq.c251 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_log_hubp_states()