| /linux-6.12.1/drivers/phy/mediatek/ |
| D | phy-mtk-hdmi-mt8195.c | 213 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; in mtk_hdmi_pll_calc() local
218 pixel_clk = rate; in mtk_hdmi_pll_calc()
219 tmds_clk = pixel_clk; in mtk_hdmi_pll_calc()
291 digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); in mtk_hdmi_pll_calc()
307 u32 pixel_clk = hdmi_phy->pll_rate; in mtk_hdmi_pll_drv_setting() local
309 tmds_clk = pixel_clk; in mtk_hdmi_pll_drv_setting()
327 } else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) { in mtk_hdmi_pll_drv_setting()
332 } else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) { in mtk_hdmi_pll_drv_setting()
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_audio.c | 440 unsigned int h_active, h_total, hblank_delta, pixel_clk; in calc_hblank_early_prog() local
447 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; in calc_hblank_early_prog()
459 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) in calc_hblank_early_prog()
462 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; in calc_hblank_early_prog()
463 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); in calc_hblank_early_prog()
468 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
471 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), in calc_hblank_early_prog()
474 mul_u32_u32(64 * pixel_clk, 1000000)); in calc_hblank_early_prog()
477 …hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_… in calc_hblank_early_prog()
484 unsigned int h_active, h_total, pixel_clk; in calc_samples_room() local
[all …]
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| /linux-6.12.1/drivers/media/platform/cadence/ |
| D | cdns-csi2rx.c | 87 struct clk *pixel_clk[CSI2RX_STREAMS_MAX]; member
271 ret = clk_prepare_enable(csi2rx->pixel_clk[i]); in csi2rx_start()
310 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); in csi2rx_start()
347 clk_disable_unprepare(csi2rx->pixel_clk[i]); in csi2rx_stop()
591 csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name); in csi2rx_get_resources()
592 if (IS_ERR(csi2rx->pixel_clk[i])) { in csi2rx_get_resources()
594 return PTR_ERR(csi2rx->pixel_clk[i]); in csi2rx_get_resources()
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| D | cdns-csi2tx.c | 108 struct clk *pixel_clk[CSI2TX_STREAMS_MAX]; member
485 csi2tx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name); in csi2tx_get_resources()
486 if (IS_ERR(csi2tx->pixel_clk[i])) { in csi2tx_get_resources()
489 return PTR_ERR(csi2tx->pixel_clk[i]); in csi2tx_get_resources()
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| /linux-6.12.1/drivers/gpu/drm/mediatek/ |
| D | mtk_dpi.c | 72 struct clk *pixel_clk; member
473 clk_disable_unprepare(dpi->pixel_clk); in mtk_dpi_power_off()
490 ret = clk_prepare_enable(dpi->pixel_clk); in mtk_dpi_power_on()
539 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); in mtk_dpi_set_display_mode()
541 clk_set_rate(dpi->pixel_clk, vm.pixelclock); in mtk_dpi_set_display_mode()
544 vm.pixelclock = clk_get_rate(dpi->pixel_clk); in mtk_dpi_set_display_mode()
1047 dpi->pixel_clk = devm_clk_get(dev, "pixel"); in mtk_dpi_probe()
1048 if (IS_ERR(dpi->pixel_clk)) in mtk_dpi_probe()
1049 return dev_err_probe(dev, PTR_ERR(dpi->pixel_clk), in mtk_dpi_probe()
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| /linux-6.12.1/drivers/gpu/drm/stm/ |
| D | ltdc.c | 838 result = clk_round_rate(ldev->pixel_clk, target); in ltdc_crtc_mode_valid()
874 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { in ltdc_crtc_mode_fixup()
879 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; in ltdc_crtc_mode_fixup()
1874 clk_disable_unprepare(ldev->pixel_clk); in ltdc_suspend()
1884 ret = clk_prepare_enable(ldev->pixel_clk); in ltdc_resume()
1914 ldev->pixel_clk = devm_clk_get(dev, "lcd"); in ltdc_load()
1915 if (IS_ERR(ldev->pixel_clk)) { in ltdc_load()
1916 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) in ltdc_load()
1918 return PTR_ERR(ldev->pixel_clk); in ltdc_load()
1921 if (clk_prepare_enable(ldev->pixel_clk)) { in ltdc_load()
[all …]
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| D | ltdc.h | 46 struct clk *pixel_clk; /* lcd pixel clock */ member
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| /linux-6.12.1/drivers/gpu/drm/bridge/synopsys/ |
| D | dw-hdmi.c | 561 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) in hdmi_compute_n() argument
573 if (pixel_clk == 25175000) in hdmi_compute_n()
575 else if (pixel_clk == 27027000) in hdmi_compute_n()
577 else if (pixel_clk == 74176000 || pixel_clk == 148352000) in hdmi_compute_n()
579 else if (pixel_clk == 297000000) in hdmi_compute_n()
587 if (pixel_clk == 25175000) in hdmi_compute_n()
589 else if (pixel_clk == 74176000) in hdmi_compute_n()
591 else if (pixel_clk == 148352000) in hdmi_compute_n()
593 else if (pixel_clk == 297000000) in hdmi_compute_n()
601 if (pixel_clk == 25175000) in hdmi_compute_n()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/msm/dsi/ |
| D | dsi_host.c | 119 struct clk *pixel_clk; member
299 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); in dsi_clk_init()
300 if (IS_ERR(msm_host->pixel_clk)) { in dsi_clk_init()
301 ret = PTR_ERR(msm_host->pixel_clk); in dsi_clk_init()
304 msm_host->pixel_clk = NULL; in dsi_clk_init()
365 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_6g()
400 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
416 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
451 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_v2()
482 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_v2()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/msm/dp/ |
| D | dp_ctrl.c | 89 struct clk *pixel_clk; member
1725 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in dp_ctrl_process_phy_test_request()
1734 ret = clk_prepare_enable(ctrl->pixel_clk); in dp_ctrl_process_phy_test_request()
1979 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in dp_ctrl_on_stream()
1988 ret = clk_prepare_enable(ctrl->pixel_clk); in dp_ctrl_on_stream()
2047 clk_disable_unprepare(ctrl->pixel_clk); in dp_ctrl_off_link_stream()
2100 clk_disable_unprepare(ctrl->pixel_clk); in dp_ctrl_off()
2200 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); in dp_ctrl_clk_init()
2201 if (IS_ERR(ctrl->pixel_clk)) in dp_ctrl_clk_init()
2202 return PTR_ERR(ctrl->pixel_clk); in dp_ctrl_clk_init()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/ |
| D | clock_source.h | 180 unsigned int pixel_clk,
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| /linux-6.12.1/drivers/gpu/drm/aspeed/ |
| D | aspeed_gfx_crtc.c | 93 clk_set_rate(priv->pixel_clk, m->crtc_clock * 1000); in aspeed_gfx_crtc_mode_set_nofb()
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| /linux-6.12.1/drivers/gpu/ipu-v3/ |
| D | ipu-csi.c | 192 static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk, in ipu_csi_set_testgen_mclk() argument
198 div_ratio = (ipu_clk / pixel_clk) - 1; in ipu_csi_set_testgen_mclk()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/include/ |
| D | grph_object_ctrl_defs.h | 128 uint32_t pixel_clk; /* in KHz */ member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/bios/ |
| D | command_table.c | 1542 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v2() local
1546 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v2()
1592 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v3() local
1596 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v3()
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| D | bios_parser.c | 1246 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_2()
1364 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_3()
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| D | bios_parser2.c | 1456 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; in get_embedded_panel_info_v2_1()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.c | 1303 unsigned int pixel_clk, in dcn20_override_dp_pix_clk() argument
1309 REG_WRITE(PHASE[inst], pixel_clk); in dcn20_override_dp_pix_clk()
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| /linux-6.12.1/drivers/gpu/drm/i915/gvt/ |
| D | handlers.c | 684 u64 pixel_clk = 0; in vgpu_update_refresh_rate() local
689 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); in vgpu_update_refresh_rate()
690 pixel_clk *= MSEC_PER_SEC; in vgpu_update_refresh_rate()
693 …new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal… in vgpu_update_refresh_rate()
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