Searched refs:native_wrmsrl (Results 1 – 7 of 7) sorted by relevance
| /linux-6.12.1/arch/x86/include/asm/ |
| D | microcode.h | 64 native_wrmsrl(MSR_IA32_UCODE_REV, 0); in intel_get_microcode_revision()
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| D | spec-ctrl.h | 87 native_wrmsrl(MSR_IA32_SPEC_CTRL, val); in __update_spec_ctrl()
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| D | msr.h | 112 #define native_wrmsrl(msr, val) \ macro
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| /linux-6.12.1/arch/x86/kernel/cpu/microcode/ |
| D | intel.c | 329 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); in __apply_microcode()
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| D | amd.c | 490 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc->hdr.data_code); in __apply_microcode_amd()
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| /linux-6.12.1/arch/x86/hyperv/ |
| D | ivm.c | 119 native_wrmsrl(MSR_AMD64_SEV_ES_GHCB, val); in wr_ghcb_msr()
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| /linux-6.12.1/arch/x86/kvm/vmx/ |
| D | vmx.c | 385 native_wrmsrl(MSR_IA32_MCU_OPT_CTRL, msr); in vmx_disable_fb_clear()
396 native_wrmsrl(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl); in vmx_enable_fb_clear()
6692 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); in vmx_l1d_flush()
7253 native_wrmsrl(MSR_IA32_SPEC_CTRL, hostval); in vmx_spec_ctrl_restore_host()
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