Searched refs:mpll_cfg (Results 1 – 10 of 10) sorted by relevance
254 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; in dw_hdmi_rockchip_mode_valid() local270 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { in dw_hdmi_rockchip_mode_valid()275 if (exact_match && pclk == mpll_cfg[i].mpixelclock) in dw_hdmi_rockchip_mode_valid()281 if (!exact_match && pclk <= mpll_cfg[i].mpixelclock) in dw_hdmi_rockchip_mode_valid()473 .mpll_cfg = rockchip_mpll_cfg,510 .mpll_cfg = rockchip_mpll_cfg,524 .mpll_cfg = rockchip_mpll_cfg,
53 static struct mpll_cfg dcn21_mpll_cfg_ref[] = {185 cfg->mpll_cfg = dcn21_mpll_cfg_ref[0]; in update_cfg_data()188 cfg->mpll_cfg = dcn21_mpll_cfg_ref[1]; in update_cfg_data()191 cfg->mpll_cfg = dcn21_mpll_cfg_ref[2]; in update_cfg_data()194 cfg->mpll_cfg = dcn21_mpll_cfg_ref[3]; in update_cfg_data()
58 static struct mpll_cfg dcn2_mpll_cfg[] = {225 cfg->mpll_cfg = dcn2_mpll_cfg[0]; in update_cfg_data()228 cfg->mpll_cfg = dcn2_mpll_cfg[1]; in update_cfg_data()231 cfg->mpll_cfg = dcn2_mpll_cfg[2]; in update_cfg_data()234 cfg->mpll_cfg = dcn2_mpll_cfg[3]; in update_cfg_data()
249 struct mpll_cfg { struct292 struct mpll_cfg mpll_cfg; argument
167 .mpll_cfg = imx_mpll_cfg,174 .mpll_cfg = imx_mpll_cfg,
61 .mpll_cfg = ingenic_mpll_cfg,
584 plat_data->mpll_cfg = variant->mpll_cfg; in sun8i_hdmi_phy_set_ops()624 .mpll_cfg = sun50i_h6_mpll_cfg,
154 const struct dw_hdmi_mpll_config *mpll_cfg; member
158 const struct dw_hdmi_mpll_config *mpll_cfg; member
1573 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; in hdmi_phy_configure_dwc_hdmi_3d_tx()