Home
last modified time | relevance | path

Searched refs:mmUVD_RB_WPTR4 (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h226 #define mmUVD_RB_WPTR4 macro
Dvcn_2_5_offset.h589 #define mmUVD_RB_WPTR4 macro
Dvcn_2_0_0_offset.h940 #define mmUVD_RB_WPTR4 macro
Dvcn_3_0_0_offset.h919 #define mmUVD_RB_WPTR4 macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
Dvcn_v2_0.c79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
Dvcn_v2_5.c82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
Dvcn_v3_0.c86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),