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Searched refs:mmUVD_DPG_PAUSE (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
1267 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & in vcn_v1_0_pause_dpg_mode()
1281 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v1_0_pause_dpg_mode()
1282 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v1_0_pause_dpg_mode()
1311 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v1_0_pause_dpg_mode()
1323 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & in vcn_v1_0_pause_dpg_mode()
1342 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v1_0_pause_dpg_mode()
1343 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v1_0_pause_dpg_mode()
1372 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v1_0_pause_dpg_mode()
Dvcn_v2_0.c89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
1256 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & in vcn_v2_0_pause_dpg_mode()
1267 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_0_pause_dpg_mode()
1270 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v2_0_pause_dpg_mode()
1314 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_0_pause_dpg_mode()
Dvcn_v2_5.c92 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
1507 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v2_5_pause_dpg_mode()
1519 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
1522 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v2_5_pause_dpg_mode()
1561 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
Dvcn_v3_0.c96 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
1655 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v3_0_pause_dpg_mode()
1665 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v3_0_pause_dpg_mode()
1668 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v3_0_pause_dpg_mode()
1716 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v3_0_pause_dpg_mode()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h42 #define mmUVD_DPG_PAUSE … macro
Dvcn_2_5_offset.h415 #define mmUVD_DPG_PAUSE … macro
Dvcn_2_0_0_offset.h400 #define mmUVD_DPG_PAUSE … macro
Dvcn_3_0_0_offset.h691 #define mmUVD_DPG_PAUSE … macro