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Searched refs:mmUVD_DPG_LMA_DATA (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vcn.h88 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
93 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
148 mmUVD_DPG_LMA_DATA, value); \
Damdgpu_jpeg.h39 mmUVD_DPG_LMA_DATA, value); \
60 RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \
Djpeg_v4_0_5.c39 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA macro
Dvcn_v4_0_5.c44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA macro
Dvcn_v4_0_3.c42 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA macro
Dvcn_v1_0.c79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
Dvcn_v2_0.c87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
Dvcn_v4_0.c44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA macro
Dvcn_v2_5.c90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
Dvcn_v3_0.c94 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h38 #define mmUVD_DPG_LMA_DATA macro
Dvcn_2_5_offset.h411 #define mmUVD_DPG_LMA_DATA macro
Dvcn_2_0_0_offset.h396 #define mmUVD_DPG_LMA_DATA macro
Dvcn_3_0_0_offset.h687 #define mmUVD_DPG_LMA_DATA macro