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Searched refs:mec_int_cntl_reg (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_3.c3075 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state() local
3086 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3089 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3092 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3095 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3108 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3111 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3114 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3117 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3154 u32 mec_int_cntl_reg, mec_int_cntl; in gfx_v9_4_3_set_priv_reg_fault_state() local
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Dgfx_v7_0.c4647 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v7_0_set_compute_eop_interrupt_state() local
4658 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4661 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4664 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4667 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4680 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4682 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
4685 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4687 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6436 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v8_0_set_compute_eop_interrupt_state() local
6447 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6450 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6453 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6456 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6469 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6471 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
6474 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6476 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
Dgfx_v12_0.c4683 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v12_0_set_compute_eop_interrupt_state() local
4694 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
4697 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
4710 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4715 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
4718 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4723 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
Dgfx_v11_0.c6149 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v11_0_set_compute_eop_interrupt_state() local
6160 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6163 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6166 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6169 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6182 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6187 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6190 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6195 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
Dgfx_v9_0.c5960 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_0_set_compute_eop_interrupt_state() local
5971 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5974 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5977 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5980 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5993 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
5996 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
5999 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
6002 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v10_0.c9003 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v10_0_set_compute_eop_interrupt_state() local
9014 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9017 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9020 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9023 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9036 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9039 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9042 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9045 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()