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Searched refs:lane_settings (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_dp_training.c303 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in maximize_lane_settings()
308 max_requested.VOLTAGE_SWING = lane_settings[0].VOLTAGE_SWING; in maximize_lane_settings()
309 max_requested.PRE_EMPHASIS = lane_settings[0].PRE_EMPHASIS; in maximize_lane_settings()
310 max_requested.FFE_PRESET = lane_settings[0].FFE_PRESET; in maximize_lane_settings()
314 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING) in maximize_lane_settings()
315 max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING; in maximize_lane_settings()
317 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS) in maximize_lane_settings()
318 max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS; in maximize_lane_settings()
319 if (lane_settings[lane].FFE_PRESET.settings.level > in maximize_lane_settings()
322 lane_settings[lane].FFE_PRESET.settings.level; in maximize_lane_settings()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/hwss/
Dlink_hwss_hpo_fixed_vs_pe_retimer_dp.c179 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_hpo_fixed_vs_pe_retimer_dp_lane_settings()
185 dp_hpo_fixed_vs_pe_retimer_set_tx_ffe(link, &lane_settings[0]); in set_hpo_fixed_vs_pe_retimer_dp_lane_settings()
191 lane_settings[0].FFE_PRESET.raw); in set_hpo_fixed_vs_pe_retimer_dp_lane_settings()
Dlink_hwss_hpo_dp.c161 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_hpo_dp_lane_settings()
166 lane_settings[0].FFE_PRESET.raw); in set_hpo_dp_lane_settings()
Dlink_hwss_dio.h54 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
Dlink_hwss_dio.c185 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_dio_dp_lane_settings()
189 link_enc->funcs->dp_set_lane_settings(link_enc, link_settings, lane_settings); in set_dio_dp_lane_settings()
Dlink_hwss_dpia.c76 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_dio_dpia_lane_settings()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/
Dlink_hwss.h65 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/virtual/
Dvirtual_link_encoder.c65 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {} in virtual_link_encoder_dp_set_lane_settings()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/
Ddcn10_link_encoder.c1101 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in dcn10_link_encoder_dp_set_lane_settings()
1125 lane_settings[lane].VOLTAGE_SWING; in dcn10_link_encoder_dp_set_lane_settings()
1127 lane_settings[lane].PRE_EMPHASIS; in dcn10_link_encoder_dp_set_lane_settings()
1135 lane_settings[lane].POST_CURSOR2; in dcn10_link_encoder_dp_set_lane_settings()
1139 cntl.lane_settings = training_lane_set.raw; in dcn10_link_encoder_dp_set_lane_settings()
Ddcn10_link_encoder.h618 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.c1323 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in dce110_link_encoder_dp_set_lane_settings()
1347 lane_settings[lane].VOLTAGE_SWING; in dce110_link_encoder_dp_set_lane_settings()
1349 lane_settings[lane].PRE_EMPHASIS; in dce110_link_encoder_dp_set_lane_settings()
1357 lane_settings[lane].POST_CURSOR2; in dce110_link_encoder_dp_set_lane_settings()
1361 cntl.lane_settings = training_lane_set.raw; in dce110_link_encoder_dp_set_lane_settings()
Ddce_link_encoder.h283 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/
Dlink_encoder.h133 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
/linux-6.12.1/drivers/gpu/drm/amd/display/include/
Dbios_parser_types.h163 uint32_t lane_settings; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/bios/
Dcommand_table.c473 params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings; in transmitter_control_v2()
602 params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings; in transmitter_control_v3()
735 params.asMode.ucLaneSet = (uint8_t)(cntl->lane_settings); in transmitter_control_v4()
832 params.ucDPLaneSet = (uint8_t) cntl->lane_settings; in transmitter_control_v1_5()
882 params.ucDPLaneSet = (uint8_t)cntl->lane_settings; in transmitter_control_v1_6()
Dcommand_table2.c278 ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings; in transmitter_control_v1_6()
345 dig_v1_7.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings; in transmitter_control_v1_7()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
Ddcn31_hpo_dp_link_encoder.c586 cntl.lane_settings = ffe_preset; in dcn31_hpo_dp_link_enc_set_ffe()