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/linux-6.12.1/drivers/hwmon/
Ddme1737.c74 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \ argument
75 (ix) < 7 ? 0x94 + (ix) : \
77 #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \ argument
78 : 0x91 + (ix) * 2)
79 #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \ argument
80 : 0x92 + (ix) * 2)
83 #define DME1737_REG_TEMP(ix) (0x25 + (ix)) argument
84 #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2) argument
85 #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2) argument
86 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \ argument
[all …]
Dvt1211.c62 #define VT1211_REG_IN(ix) (0x21 + (ix)) argument
63 #define VT1211_REG_IN_MIN(ix) ((ix) == 0 ? 0x3e : 0x2a + 2 * (ix)) argument
64 #define VT1211_REG_IN_MAX(ix) ((ix) == 0 ? 0x3d : 0x29 + 2 * (ix)) argument
72 #define VT1211_REG_FAN(ix) (0x29 + (ix)) argument
73 #define VT1211_REG_FAN_MIN(ix) (0x3b + (ix)) argument
78 #define VT1211_REG_PWM(ix) (0x60 + (ix)) argument
82 #define VT1211_REG_PWM_AUTO_PWM(ix, ap) (0x58 + 2 * (ix) - (ap)) argument
134 #define ISVOLT(ix, uch_config) ((ix) > 4 ? 1 : \ argument
135 !(((uch_config) >> ((ix) + 2)) & 1))
138 #define ISTEMP(ix, uch_config) ((ix) < 2 ? 1 : \ argument
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh2a/
Dfpu.c96 unsigned int ix, iy; in denormal_mulf() local
100 ix = hx & 0x7fffffff; in denormal_mulf()
102 if (iy < 0x00800000 || ix == 0) in denormal_mulf()
106 ix &= 0x007fffff; in denormal_mulf()
108 m = (unsigned long long)ix * iy; in denormal_mulf()
116 ix = ((int) (m >> (w - 23)) & 0x007fffff) | (exp << 23); in denormal_mulf()
118 ix = (int) (m >> (w - 22 - exp)) & 0x007fffff; in denormal_mulf()
120 ix = 0; in denormal_mulf()
122 ix |= (hx ^ hy) & 0x80000000; in denormal_mulf()
123 return ix; in denormal_mulf()
[all …]
/linux-6.12.1/io_uring/
Dxattr.c27 struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); in io_xattr_cleanup() local
29 if (ix->filename) in io_xattr_cleanup()
30 putname(ix->filename); in io_xattr_cleanup()
32 kfree(ix->ctx.kname); in io_xattr_cleanup()
33 kvfree(ix->ctx.kvalue); in io_xattr_cleanup()
47 struct io_xattr *ix = io_kiocb_to_cmd(req, struct io_xattr); in __io_getxattr_prep() local
54 ix->filename = NULL; in __io_getxattr_prep()
55 ix->ctx.kvalue = NULL; in __io_getxattr_prep()
57 ix->ctx.cvalue = u64_to_user_ptr(READ_ONCE(sqe->addr2)); in __io_getxattr_prep()
58 ix->ctx.size = READ_ONCE(sqe->len); in __io_getxattr_prep()
[all …]
/linux-6.12.1/arch/mips/math-emu/
Dsp_sqrt.c14 int ix, s, q, m, t, i; in ieee754sp_sqrt() local
56 ix = x.bits; in ieee754sp_sqrt()
59 m = (ix >> 23); in ieee754sp_sqrt()
61 for (i = 0; (ix & 0x00800000) == 0; i++) in ieee754sp_sqrt()
62 ix <<= 1; in ieee754sp_sqrt()
66 ix = (ix & 0x007fffff) | 0x00800000; in ieee754sp_sqrt()
68 ix += ix; in ieee754sp_sqrt()
72 ix += ix; in ieee754sp_sqrt()
79 if (t <= ix) { in ieee754sp_sqrt()
81 ix -= t; in ieee754sp_sqrt()
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/en/
Drx_res.c335 int ix; in mlx5e_rx_res_channels_init() local
347 for (ix = 0; ix < res->max_nch; ix++) { in mlx5e_rx_res_channels_init()
348 err = mlx5e_rqt_init_direct(&res->channels[ix].direct_rqt, in mlx5e_rx_res_channels_init()
353 err, ix); in mlx5e_rx_res_channels_init()
358 for (ix = 0; ix < res->max_nch; ix++) { in mlx5e_rx_res_channels_init()
360 mlx5e_rqt_get_rqtn(&res->channels[ix].direct_rqt), in mlx5e_rx_res_channels_init()
365 err = mlx5e_tir_init(&res->channels[ix].direct_tir, builder, res->mdev, true); in mlx5e_rx_res_channels_init()
368 err, ix); in mlx5e_rx_res_channels_init()
378 while (--ix >= 0) in mlx5e_rx_res_channels_init()
379 mlx5e_tir_destroy(&res->channels[ix].direct_tir); in mlx5e_rx_res_channels_init()
[all …]
Dchannels.c14 static struct mlx5e_channel *mlx5e_channels_get(struct mlx5e_channels *chs, unsigned int ix) in mlx5e_channels_get() argument
16 WARN_ON_ONCE(ix >= mlx5e_channels_get_num(chs)); in mlx5e_channels_get()
17 return chs->c[ix]; in mlx5e_channels_get()
20 bool mlx5e_channels_is_xsk(struct mlx5e_channels *chs, unsigned int ix) in mlx5e_channels_is_xsk() argument
22 struct mlx5e_channel *c = mlx5e_channels_get(chs, ix); in mlx5e_channels_is_xsk()
27 void mlx5e_channels_get_regular_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn, in mlx5e_channels_get_regular_rqn() argument
30 struct mlx5e_channel *c = mlx5e_channels_get(chs, ix); in mlx5e_channels_get_regular_rqn()
37 void mlx5e_channels_get_xsk_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn, in mlx5e_channels_get_xsk_rqn() argument
40 struct mlx5e_channel *c = mlx5e_channels_get(chs, ix); in mlx5e_channels_get_xsk_rqn()
Dfs_tt_redirect.c148 int ix = 0; in fs_udp_create_groups() local
178 MLX5_SET_CFG(in, start_flow_index, ix); in fs_udp_create_groups()
179 ix += MLX5E_FS_UDP_GROUP1_SIZE; in fs_udp_create_groups()
180 MLX5_SET_CFG(in, end_flow_index, ix - 1); in fs_udp_create_groups()
188 MLX5_SET_CFG(in, start_flow_index, ix); in fs_udp_create_groups()
189 ix += MLX5E_FS_UDP_GROUP2_SIZE; in fs_udp_create_groups()
190 MLX5_SET_CFG(in, end_flow_index, ix - 1); in fs_udp_create_groups()
430 int ix = 0; in fs_any_create_groups() local
449 MLX5_SET_CFG(in, start_flow_index, ix); in fs_any_create_groups()
450 ix += MLX5E_FS_ANY_GROUP1_SIZE; in fs_any_create_groups()
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/
Dpool.c46 static int mlx5e_xsk_add_pool(struct mlx5e_xsk *xsk, struct xsk_buff_pool *pool, u16 ix) in mlx5e_xsk_add_pool() argument
54 xsk->pools[ix] = pool; in mlx5e_xsk_add_pool()
58 static void mlx5e_xsk_remove_pool(struct mlx5e_xsk *xsk, u16 ix) in mlx5e_xsk_remove_pool() argument
60 xsk->pools[ix] = NULL; in mlx5e_xsk_remove_pool()
79 struct xsk_buff_pool *pool, u16 ix) in mlx5e_xsk_enable_locked() argument
86 if (unlikely(mlx5e_xsk_get_pool(&priv->channels.params, &priv->xsk, ix))) in mlx5e_xsk_enable_locked()
92 err = mlx5e_xsk_map_pool(mlx5_sd_ch_ix_get_dev(priv->mdev, ix), pool); in mlx5e_xsk_enable_locked()
96 err = mlx5e_xsk_add_pool(&priv->xsk, pool, ix); in mlx5e_xsk_enable_locked()
123 c = priv->channels.c[ix]; in mlx5e_xsk_enable_locked()
136 mlx5e_rx_res_xsk_update(priv->rx_res, &priv->channels, ix, true); in mlx5e_xsk_enable_locked()
[all …]
Dpool.h10 struct mlx5e_xsk *xsk, u16 ix) in mlx5e_xsk_get_pool() argument
15 if (unlikely(ix >= params->num_channels)) in mlx5e_xsk_get_pool()
18 return xsk->pools[ix]; in mlx5e_xsk_get_pool()
Drx.c19 int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) in mlx5e_xsk_alloc_rx_mpwqe() argument
21 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, ix); in mlx5e_xsk_alloc_rx_mpwqe()
130 offset = ix * rq->mpwqe.mtts_per_wqe; in mlx5e_xsk_alloc_rx_mpwqe()
160 int mlx5e_xsk_alloc_rx_wqes_batched(struct mlx5e_rq *rq, u16 ix, int wqe_bulk) in mlx5e_xsk_alloc_rx_wqes_batched() argument
171 contig = mlx5_wq_cyc_get_size(wq) - ix; in mlx5e_xsk_alloc_rx_wqes_batched()
173 alloc = xsk_buff_alloc_batch(rq->xsk_pool, buffs + ix, wqe_bulk); in mlx5e_xsk_alloc_rx_wqes_batched()
175 alloc = xsk_buff_alloc_batch(rq->xsk_pool, buffs + ix, contig); in mlx5e_xsk_alloc_rx_wqes_batched()
181 int j = mlx5_wq_cyc_ctr2ix(wq, ix + i); in mlx5e_xsk_alloc_rx_wqes_batched()
198 int mlx5e_xsk_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, int wqe_bulk) in mlx5e_xsk_alloc_rx_wqes() argument
204 int j = mlx5_wq_cyc_ctr2ix(wq, ix + i); in mlx5e_xsk_alloc_rx_wqes()
Drx.h11 int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
12 int mlx5e_xsk_alloc_rx_wqes_batched(struct mlx5e_rq *rq, u16 ix, int wqe_bulk);
13 int mlx5e_xsk_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, int wqe_bulk);
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/
Dwq.h82 void mlx5_wq_cyc_wqe_dump(struct mlx5_wq_cyc *wq, u16 ix, u8 nstrides);
157 static inline void *mlx5_wq_cyc_get_wqe(struct mlx5_wq_cyc *wq, u16 ix) in mlx5_wq_cyc_get_wqe() argument
159 return mlx5_frag_buf_get_wqe(&wq->fbc, ix); in mlx5_wq_cyc_get_wqe()
162 static inline u16 mlx5_wq_cyc_get_contig_wqebbs(struct mlx5_wq_cyc *wq, u16 ix) in mlx5_wq_cyc_get_contig_wqebbs() argument
164 return mlx5_frag_buf_get_idx_last_contig_stride(&wq->fbc, ix) - ix + 1; in mlx5_wq_cyc_get_contig_wqebbs()
200 static inline struct mlx5_cqe64 *mlx5_cqwq_get_wqe(struct mlx5_cqwq *wq, u32 ix) in mlx5_cqwq_get_wqe() argument
202 struct mlx5_cqe64 *cqe = mlx5_frag_buf_get_wqe(&wq->fbc, ix); in mlx5_cqwq_get_wqe()
283 static inline void *mlx5_wq_ll_get_wqe(struct mlx5_wq_ll *wq, u16 ix) in mlx5_wq_ll_get_wqe() argument
285 return mlx5_frag_buf_get_wqe(&wq->fbc, ix); in mlx5_wq_ll_get_wqe()
288 static inline u16 mlx5_wq_ll_get_wqe_next_ix(struct mlx5_wq_ll *wq, u16 ix) in mlx5_wq_ll_get_wqe_next_ix() argument
[all …]
/linux-6.12.1/fs/qnx4/
Ddir.c24 int ix, ino; in qnx4_readdir() local
37 ix = (ctx->pos >> QNX4_DIR_ENTRY_SIZE_BITS) % QNX4_INODES_PER_BLOCK; in qnx4_readdir()
38 for (; ix < QNX4_INODES_PER_BLOCK; ix++, ctx->pos += QNX4_DIR_ENTRY_SIZE) { in qnx4_readdir()
42 offset = ix * QNX4_DIR_ENTRY_SIZE; in qnx4_readdir()
50 ino = blknum * QNX4_INODES_PER_BLOCK + ix - 1; in qnx4_readdir()
/linux-6.12.1/arch/s390/lib/
Dspinlock.c63 int ix; in arch_spin_lock_setup() local
66 for (ix = 0; ix < 4; ix++, node++) { in arch_spin_lock_setup()
69 (ix << _Q_TAIL_IDX_OFFSET); in arch_spin_lock_setup()
99 int ix, cpu; in arch_spin_decode_tail() local
101 ix = (lock & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET; in arch_spin_decode_tail()
103 return per_cpu_ptr(&spin_wait[ix], cpu - 1); in arch_spin_decode_tail()
120 int lockval, ix, node_id, tail_id, old, new, owner, count; in arch_spin_lock_queued() local
122 ix = get_lowcore()->spinlock_index++; in arch_spin_lock_queued()
125 node = this_cpu_ptr(&spin_wait[ix]); in arch_spin_lock_queued()
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dfs_ttc.c374 int ix = 0; in mlx5_create_ttc_table_groups() local
399 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
400 ix += groups->group_size[ttc->num_groups]; in mlx5_create_ttc_table_groups()
401 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_groups()
412 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
413 ix += groups->group_size[ttc->num_groups]; in mlx5_create_ttc_table_groups()
414 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_groups()
422 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
423 ix += groups->group_size[ttc->num_groups]; in mlx5_create_ttc_table_groups()
424 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_groups()
[all …]
Dmpfs.h53 int ix = MLX5_L2_ADDR_HASH(mac); \
57 hlist_for_each_entry(ptr, &(hash)[ix], node.hlist) \
68 int ix = MLX5_L2_ADDR_HASH(mac); \
74 hlist_add_head(&ptr->node.hlist, &(hash)[ix]);\
Dmpfs.c79 static int alloc_l2table_index(struct mlx5_mpfs *l2table, u32 *ix) in alloc_l2table_index() argument
83 *ix = find_first_zero_bit(l2table->bitmap, l2table->size); in alloc_l2table_index()
84 if (*ix >= l2table->size) in alloc_l2table_index()
87 __set_bit(*ix, l2table->bitmap); in alloc_l2table_index()
92 static void free_l2table_index(struct mlx5_mpfs *l2table, u32 ix) in free_l2table_index() argument
94 __clear_bit(ix, l2table->bitmap); in free_l2table_index()
Dipsec_fs_roce.c343 int ix = 0; in ipsec_fs_roce_tx_mpv_create_group_rules() local
351 MLX5_SET_CFG(in, start_flow_index, ix); in ipsec_fs_roce_tx_mpv_create_group_rules()
352 ix += MLX5_TX_ROCE_GROUP_SIZE; in ipsec_fs_roce_tx_mpv_create_group_rules()
353 MLX5_SET_CFG(in, end_flow_index, ix - 1); in ipsec_fs_roce_tx_mpv_create_group_rules()
448 int ix = 0; in ipsec_fs_roce_rx_mpv_create() local
506 MLX5_SET_CFG(in, start_flow_index, ix); in ipsec_fs_roce_rx_mpv_create()
507 ix += 1; in ipsec_fs_roce_rx_mpv_create()
508 MLX5_SET_CFG(in, end_flow_index, ix - 1); in ipsec_fs_roce_rx_mpv_create()
605 int ix = 0; in mlx5_ipsec_fs_roce_tx_create() local
635 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_ipsec_fs_roce_tx_create()
[all …]
/linux-6.12.1/drivers/media/dvb-frontends/
Dmxl692.c196 u32 ix, div_size; in mxl692_checksum() local
203 for (ix = 0; ix < div_size; ix++) in mxl692_checksum()
204 cur_cksum += be32_to_cpu(buf[ix]); in mxl692_checksum()
215 u32 ix, temp; in mxl692_validate_fw_header() local
235 for (ix = 16; ix < buf_len; ix++) in mxl692_validate_fw_header()
236 temp_cksum += buffer[ix]; in mxl692_validate_fw_header()
251 u32 ix = 0, total_len = 0, addr = 0, chunk_len = 0, prevchunk_len = 0; in mxl692_write_fw_block() local
255 ix = *index; in mxl692_write_fw_block()
257 if (buffer[ix] == 0x53) { in mxl692_write_fw_block()
258 total_len = buffer[ix + 1] << 16 | buffer[ix + 2] << 8 | buffer[ix + 3]; in mxl692_write_fw_block()
[all …]
/linux-6.12.1/drivers/input/misc/
Dyealink.c284 int ix, len; in yealink_set_ringtone() local
300 ix = 0; in yealink_set_ringtone()
301 while (size != ix) { in yealink_set_ringtone()
302 len = size - ix; in yealink_set_ringtone()
306 p->offset = cpu_to_be16(ix); in yealink_set_ringtone()
307 memcpy(p->data, &buf[ix], len); in yealink_set_ringtone()
309 ix += len; in yealink_set_ringtone()
319 int i, ix, len; in yealink_do_idle_tasks() local
321 ix = yld->stat_ix; in yealink_do_idle_tasks()
329 if (ix >= sizeof(yld->master)) { in yealink_do_idle_tasks()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu_helper.h155 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
159 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
167 cgs_write_ind_register(device, port, ix##reg, \
168 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
172 cgs_write_ind_register(device, port, ix##reg, \
173 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
181 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
192 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
206 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
220 PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
/linux-6.12.1/fs/ext4/
Dext4_extents.h239 static inline ext4_fsblk_t ext4_idx_pblock(struct ext4_extent_idx *ix) in ext4_idx_pblock() argument
243 block = le32_to_cpu(ix->ei_leaf_lo); in ext4_idx_pblock()
244 block |= ((ext4_fsblk_t) le16_to_cpu(ix->ei_leaf_hi) << 31) << 1; in ext4_idx_pblock()
266 static inline void ext4_idx_store_pblock(struct ext4_extent_idx *ix, in ext4_idx_store_pblock() argument
269 ix->ei_leaf_lo = cpu_to_le32((unsigned long) (pb & 0xffffffff)); in ext4_idx_store_pblock()
270 ix->ei_leaf_hi = cpu_to_le16((unsigned long) ((pb >> 31) >> 1) & in ext4_idx_store_pblock()
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dconn.c103 unsigned int ix; in mlx5_fpga_conn_post_recv() local
115 ix = conn->qp.rq.pc & (conn->qp.rq.size - 1); in mlx5_fpga_conn_post_recv()
116 data = mlx5_wq_cyc_get_wqe(&conn->qp.wq.rq, ix); in mlx5_fpga_conn_post_recv()
122 conn->qp.rq.bufs[ix] = buf; in mlx5_fpga_conn_post_recv()
146 unsigned int ix, sgi; in mlx5_fpga_conn_post_send() local
149 ix = conn->qp.sq.pc & (conn->qp.sq.size - 1); in mlx5_fpga_conn_post_send()
151 ctrl = mlx5_wq_cyc_get_wqe(&conn->qp.wq.sq, ix); in mlx5_fpga_conn_post_send()
171 conn->qp.sq.bufs[ix] = buf; in mlx5_fpga_conn_post_send()
254 int ix, err; in mlx5_fpga_conn_rq_cqe() local
256 ix = be16_to_cpu(cqe->wqe_counter) & (conn->qp.rq.size - 1); in mlx5_fpga_conn_rq_cqe()
[all …]
/linux-6.12.1/fs/netfs/
Diterator.c113 unsigned int nbv = iter->nr_segs, ix = 0, nsegs = 0; in netfs_limit_bvec() local
122 while (n && ix < nbv && skip) { in netfs_limit_bvec()
123 len = bvecs[ix].bv_len; in netfs_limit_bvec()
128 ix++; in netfs_limit_bvec()
131 while (n && ix < nbv) { in netfs_limit_bvec()
132 len = min3(n, bvecs[ix].bv_len - skip, max_size); in netfs_limit_bvec()
135 ix++; in netfs_limit_bvec()

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