| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| D | dcn10_dpp_cm.c | 421 bool is_ram_a) in dpp1_cm_configure_regamma_lut() argument
428 CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1); in dpp1_cm_configure_regamma_lut()
727 bool is_ram_a) in dpp1_program_degamma_lut() argument
736 is_ram_a == true ? 0:1); in dpp1_program_degamma_lut()
756 bool is_ram_a = true; in dpp1_set_degamma_pwl() local
760 dpp1_degamma_ram_inuse(dpp_base, &is_ram_a); in dpp1_set_degamma_pwl()
761 if (is_ram_a == true) in dpp1_set_degamma_pwl()
767 params->hw_points_num, !is_ram_a); in dpp1_set_degamma_pwl()
768 dpp1_degamma_ram_select(dpp_base, !is_ram_a); in dpp1_set_degamma_pwl()
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| D | dcn10_dpp.h | 1424 bool is_ram_a);
1470 bool is_ram_a);
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| D | dcn20_dpp_cm.c | 89 bool is_ram_a) in dpp2_program_degamma_lut() argument
97 is_ram_a == true ? 0:1); in dpp2_program_degamma_lut()
120 bool is_ram_a = true; in dpp2_set_degamma_pwl() local
124 dpp2_degamma_ram_inuse(dpp_base, &is_ram_a); in dpp2_set_degamma_pwl()
125 if (is_ram_a == true) in dpp2_set_degamma_pwl()
130 dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); in dpp2_set_degamma_pwl()
131 dpp1_degamma_ram_select(dpp_base, !is_ram_a); in dpp2_set_degamma_pwl()
378 bool is_ram_a) in dpp20_configure_blnd_lut() argument
385 CM_BLNDGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1); in dpp20_configure_blnd_lut()
617 bool is_ram_a) in dpp20_configure_shaper_lut() argument
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| D | dcn30_dpp_cm.c | 81 bool is_ram_a) in dpp3_program_gammcor_lut() argument
203 bool is_ram_a) in dpp3_configure_gamcor_lut() argument
210 CM_GAMCOR_LUT_HOST_SEL, is_ram_a == true ? 0:1); in dpp3_configure_gamcor_lut()
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| D | dcn30_dpp.c | 622 bool is_ram_a) in dpp3_configure_blnd_lut() argument
628 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1); in dpp3_configure_blnd_lut()
882 bool is_ram_a) in dpp3_configure_shaper_lut() argument
889 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); in dpp3_configure_shaper_lut()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
| D | dcn30_dwb_cm.c | 177 bool is_ram_a) in dwb3_configure_ogam_lut() argument
181 DWB_OGAM_LUT_HOST_SEL, (is_ram_a == true) ? 0 : 1); in dwb3_configure_ogam_lut()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | transform.h | 208 bool is_ram_a);
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| D | dpp.h | 262 bool is_ram_a);
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn32/ |
| D | dcn32_mpc.c | 128 bool is_ram_a) in mpc32_configure_post1dlut() argument
135 MPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1); in mpc32_configure_post1dlut()
331 bool is_ram_a, in mpc32_configure_shaper_lut() argument
339 MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); in mpc32_configure_shaper_lut()
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| D | dcn32_mpc.h | 353 bool is_ram_a);
369 bool is_ram_a,
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn20/ |
| D | dcn20_mpc.c | 285 bool is_ram_a) in mpc20_configure_ogam_lut() argument
291 MPCC_OGAM_LUT_RAM_SEL, is_ram_a == true ? 0:1); in mpc20_configure_ogam_lut()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn30/ |
| D | dcn30_mpc.c | 173 bool is_ram_a) in mpc3_configure_ogam_lut() argument
179 MPCC_OGAM_LUT_HOST_SEL, is_ram_a == true ? 0:1); in mpc3_configure_ogam_lut()
458 bool is_ram_a, in mpc3_configure_shaper_lut() argument
466 MPC_RMU_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); in mpc3_configure_shaper_lut()
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