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Searched refs:ih_rb_wptr (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dvega10_ih.c56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset()
69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); in vega10_ih_init_register_offset()
80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); in vega10_ih_init_register_offset()
125 WREG32(ih_regs->ih_rb_wptr, 0); in vega10_ih_toggle_ring_interrupts()
242 WREG32(ih_regs->ih_rb_wptr, 0); in vega10_ih_enable_ring()
356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
Dnavi10_ih.c58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset()
71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); in navi10_ih_init_register_offset()
82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); in navi10_ih_init_register_offset()
180 WREG32(ih_regs->ih_rb_wptr, 0); in navi10_ih_toggle_ring_interrupts()
298 WREG32(ih_regs->ih_rb_wptr, 0); in navi10_ih_enable_ring()
427 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in navi10_ih_get_wptr()
Dvega20_ih.c64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset()
77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); in vega20_ih_init_register_offset()
88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); in vega20_ih_init_register_offset()
134 WREG32(ih_regs->ih_rb_wptr, 0); in vega20_ih_toggle_ring_interrupts()
251 WREG32(ih_regs->ih_rb_wptr, 0); in vega20_ih_enable_ring()
408 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega20_ih_get_wptr()
Dih_v7_0.c57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v7_0_init_register_offset()
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1); in ih_v7_0_init_register_offset()
154 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v7_0_toggle_ring_interrupts()
274 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v7_0_enable_ring()
418 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v7_0_get_wptr()
Dih_v6_0.c57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_0_init_register_offset()
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1); in ih_v6_0_init_register_offset()
182 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_0_toggle_ring_interrupts()
302 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_0_enable_ring()
446 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_0_get_wptr()
Dih_v6_1.c57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_1_init_register_offset()
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1); in ih_v6_1_init_register_offset()
154 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_1_toggle_ring_interrupts()
274 WREG32(ih_regs->ih_rb_wptr, 0); in ih_v6_1_enable_ring()
418 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_1_get_wptr()
Damdgpu_ih.h40 uint32_t ih_rb_wptr; member