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Searched refs:ih_rb_rptr (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dvega10_ih.c57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset()
70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); in vega10_ih_init_register_offset()
81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); in vega10_ih_init_register_offset()
124 WREG32(ih_regs->ih_rb_rptr, 0); in vega10_ih_toggle_ring_interrupts()
243 WREG32(ih_regs->ih_rb_rptr, 0); in vega10_ih_enable_ring()
403 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega10_ih_irq_rearm()
436 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in vega10_ih_set_rptr()
Dnavi10_ih.c59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset()
72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); in navi10_ih_init_register_offset()
83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); in navi10_ih_init_register_offset()
179 WREG32(ih_regs->ih_rb_rptr, 0); in navi10_ih_toggle_ring_interrupts()
299 WREG32(ih_regs->ih_rb_rptr, 0); in navi10_ih_enable_ring()
473 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in navi10_ih_irq_rearm()
506 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in navi10_ih_set_rptr()
Dvega20_ih.c65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset()
78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); in vega20_ih_init_register_offset()
89 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); in vega20_ih_init_register_offset()
133 WREG32(ih_regs->ih_rb_rptr, 0); in vega20_ih_toggle_ring_interrupts()
252 WREG32(ih_regs->ih_rb_rptr, 0); in vega20_ih_enable_ring()
456 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega20_ih_irq_rearm()
489 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in vega20_ih_set_rptr()
Dih_v7_0.c58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v7_0_init_register_offset()
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1); in ih_v7_0_init_register_offset()
153 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v7_0_toggle_ring_interrupts()
275 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v7_0_enable_ring()
464 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v7_0_irq_rearm()
492 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in ih_v7_0_set_rptr()
Dih_v6_0.c58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_0_init_register_offset()
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1); in ih_v6_0_init_register_offset()
181 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v6_0_toggle_ring_interrupts()
303 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v6_0_enable_ring()
492 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v6_0_irq_rearm()
522 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in ih_v6_0_set_rptr()
Dih_v6_1.c58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_1_init_register_offset()
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1); in ih_v6_1_init_register_offset()
153 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v6_1_toggle_ring_interrupts()
275 WREG32(ih_regs->ih_rb_rptr, 0); in ih_v6_1_enable_ring()
465 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v6_1_irq_rearm()
495 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in ih_v6_1_set_rptr()
Damdgpu_ih.h41 uint32_t ih_rb_rptr; member