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Searched refs:hw_intf (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder_phys_vid.c20 (e) && (e)->hw_intf ? \
21 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
26 (e) && (e)->hw_intf ? \
27 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
92 if (phys_enc->hw_intf->cap->type == INTF_DSI) { in drm_mode_to_intf_timing_params()
98 if (phys_enc->hw_intf->cap->type == INTF_DP) { in drm_mode_to_intf_timing_params()
112 if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) { in drm_mode_to_intf_timing_params()
125 if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { in drm_mode_to_intf_timing_params()
175 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; in programmable_fetch_get_num_lines()
229 if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) in programmable_fetch_config()
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Ddpu_encoder_phys_cmd.c21 (e) ? (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
26 (e) ? (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
61 intf_cfg.intf = phys_enc->hw_intf->idx; in _dpu_encoder_phys_cmd_update_intf_cfg()
69 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk) in _dpu_encoder_phys_cmd_update_intf_cfg()
70 phys_enc->hw_intf->ops.bind_pingpong_blk( in _dpu_encoder_phys_cmd_update_intf_cfg()
71 phys_enc->hw_intf, in _dpu_encoder_phys_cmd_update_intf_cfg()
79 if (phys_enc->hw_intf->ops.program_intf_cmd_cfg) in _dpu_encoder_phys_cmd_update_intf_cfg()
80 phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg); in _dpu_encoder_phys_cmd_update_intf_cfg()
155 phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr; in dpu_encoder_phys_cmd_atomic_mode_set()
159 phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; in dpu_encoder_phys_cmd_atomic_mode_set()
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Ddpu_encoder.c252 return phys_enc->hw_intf->cap->type == INTF_DP && in dpu_encoder_needs_periph_flush()
292 if (phys->hw_intf && phys->hw_intf->ops.setup_misr in dpu_encoder_get_crc_values_cnt()
293 && phys->hw_intf->ops.collect_misr) in dpu_encoder_get_crc_values_cnt()
311 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) in dpu_encoder_setup_misr()
314 phys->hw_intf->ops.setup_misr(phys->hw_intf); in dpu_encoder_setup_misr()
334 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) in dpu_encoder_get_crc()
337 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]); in dpu_encoder_get_crc()
394 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, in dpu_encoder_helper_report_irq_timeout()
786 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) in _dpu_encoder_update_vsync_source()
787 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, in _dpu_encoder_update_vsync_source()
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Ddpu_rm.h31 struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0]; member
107 return rm->hw_intf[intf_idx - INTF_0]; in dpu_rm_get_intf()
Ddpu_encoder_phys.h182 struct dpu_hw_intf *hw_intf; member
265 struct dpu_hw_intf *hw_intf; member
Ddpu_rm.c107 rm->hw_intf[intf->id - INTF_0] = hw; in dpu_rm_init()