| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | vpe_v6_1.c | 76 uint32_t i, f32_cntl; in vpe_v6_1_halt() local
79 f32_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL)); in vpe_v6_1_halt()
80 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0); in vpe_v6_1_halt()
81 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, halt ? 1 : 0); in vpe_v6_1_halt()
82 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL), f32_cntl); in vpe_v6_1_halt()
159 uint32_t f32_offset, f32_cntl; in vpe_v6_1_load_microcode() local
162 f32_cntl = RREG32(f32_offset); in vpe_v6_1_load_microcode()
163 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); in vpe_v6_1_load_microcode()
164 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0); in vpe_v6_1_load_microcode()
167 adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl; in vpe_v6_1_load_microcode()
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| D | sdma_v3_0.c | 549 u32 f32_cntl, phase_quantum = 0; in sdma_v3_0_ctx_switch_enable() local
577 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
579 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
581 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
590 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
596 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_ctx_switch_enable()
610 u32 f32_cntl; in sdma_v3_0_enable() local
619 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v3_0_enable()
621 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v3_0_enable()
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| D | sdma_v2_4.c | 373 u32 f32_cntl; in sdma_v2_4_enable() local
382 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
384 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_enable()
386 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v2_4_enable()
387 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
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| D | sdma_v6_0.c | 430 u32 f32_cntl; in sdma_v6_0_ctxempty_int_enable() local
435 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); in sdma_v6_0_ctxempty_int_enable()
436 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v6_0_ctxempty_int_enable()
438 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); in sdma_v6_0_ctxempty_int_enable()
453 u32 f32_cntl; in sdma_v6_0_enable() local
465 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_enable()
466 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v6_0_enable()
467 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); in sdma_v6_0_enable()
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| D | cik_sdma.c | 342 u32 f32_cntl, phase_quantum = 0; in cik_ctx_switch_enable() local
370 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in cik_ctx_switch_enable()
372 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
381 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
385 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in cik_ctx_switch_enable()
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| D | sdma_v5_2.c | 450 u32 f32_cntl, phase_quantum = 0; in sdma_v5_2_ctx_switch_enable() local
488 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_2_ctx_switch_enable()
489 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_2_ctx_switch_enable()
491 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_2_ctx_switch_enable()
507 u32 f32_cntl; in sdma_v5_2_enable() local
517 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_enable()
518 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_2_enable()
519 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_enable()
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| D | sdma_v5_0.c | 631 u32 f32_cntl = 0, phase_quantum = 0; in sdma_v5_0_ctx_switch_enable() local
660 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_ctx_switch_enable()
661 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_0_ctx_switch_enable()
674 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_0_ctx_switch_enable()
689 u32 f32_cntl; in sdma_v5_0_enable() local
701 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_enable()
702 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_0_enable()
703 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_enable()
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| D | sdma_v4_4_2.c | 567 u32 f32_cntl, phase_quantum = 0; in sdma_v4_4_2_inst_ctx_switch_enable() local
595 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); in sdma_v4_4_2_inst_ctx_switch_enable()
596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, in sdma_v4_4_2_inst_ctx_switch_enable()
603 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); in sdma_v4_4_2_inst_ctx_switch_enable()
622 u32 f32_cntl; in sdma_v4_4_2_inst_enable() local
641 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); in sdma_v4_4_2_inst_enable()
642 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v4_4_2_inst_enable()
643 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); in sdma_v4_4_2_inst_enable()
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| D | sdma_v4_0.c | 983 u32 f32_cntl, phase_quantum = 0; in sdma_v4_0_ctx_switch_enable() local
1011 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); in sdma_v4_0_ctx_switch_enable()
1012 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v4_0_ctx_switch_enable()
1019 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); in sdma_v4_0_ctx_switch_enable()
1046 u32 f32_cntl; in sdma_v4_0_enable() local
1057 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); in sdma_v4_0_enable()
1058 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v4_0_enable()
1059 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); in sdma_v4_0_enable()
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