Searched refs:dwbc_mask (Results 1 – 10 of 10) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
| D | dcn30_dwb_cm.c | 44 dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
64 reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
71 reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam()
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| D | dcn30_dwb.c | 41 dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
261 const struct dcn30_dwbc_mask *dwbc_mask, in dcn30_dwbc_construct() argument
271 dwbc30->dwbc_mask = dwbc_mask; in dcn30_dwbc_construct()
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| D | dcn30_dwb.h | 874 const struct dcn30_dwbc_mask *dwbc_mask; member
881 const struct dcn30_dwbc_mask *dwbc_mask,
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dwb.c | 40 dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
118 const struct dcn10_dwbc_mask *dwbc_mask, in dcn10_dwbc_construct() argument
128 dwbc10->dwbc_mask = dwbc_mask; in dcn10_dwbc_construct()
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| D | dcn10_dwb.h | 257 const struct dcn10_dwbc_mask *dwbc_mask; member
264 const struct dcn10_dwbc_mask *dwbc_mask,
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dwb/dcn35/ |
| D | dcn35_dwb.c | 36 ((const struct dcn35_dwbc_mask *)(dwbc30->dwbc_mask)) \
46 const struct dcn35_dwbc_mask *dwbc_mask, in dcn35_dwbc_construct() argument
51 (const struct dcn30_dwbc_mask *)dwbc_mask, inst); in dcn35_dwbc_construct()
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| D | dcn35_dwb.h | 56 const struct dcn35_dwbc_mask *dwbc_mask,
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dwb.c | 43 dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
303 if (dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL) { in dwb2_set_scaler()
307 wbscl_mode, dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL_CURRENT, in dwb2_set_scaler()
331 const struct dcn20_dwbc_mask *dwbc_mask, in dcn20_dwbc_construct() argument
341 dwbc20->dwbc_mask = dwbc_mask; in dcn20_dwbc_construct()
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| D | dcn20_dwb.h | 392 const struct dcn20_dwbc_mask *dwbc_mask; member
399 const struct dcn20_dwbc_mask *dwbc_mask,
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| D | dcn20_dwb_scl.c | 44 dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
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