| /linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| D | dr_ste.c | 806 static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec, bool clr) in dr_ste_copy_mask_misc() argument
808 spec->gre_c_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_c_present, clr); in dr_ste_copy_mask_misc()
809 spec->gre_k_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_k_present, clr); in dr_ste_copy_mask_misc()
810 spec->gre_s_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_s_present, clr); in dr_ste_copy_mask_misc()
811 spec->source_vhca_port = IFC_GET_CLR(fte_match_set_misc, mask, source_vhca_port, clr); in dr_ste_copy_mask_misc()
812 spec->source_sqn = IFC_GET_CLR(fte_match_set_misc, mask, source_sqn, clr); in dr_ste_copy_mask_misc()
814 spec->source_port = IFC_GET_CLR(fte_match_set_misc, mask, source_port, clr); in dr_ste_copy_mask_misc()
816 IFC_GET_CLR(fte_match_set_misc, mask, source_eswitch_owner_vhca_id, clr); in dr_ste_copy_mask_misc()
818 spec->outer_second_prio = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_prio, clr); in dr_ste_copy_mask_misc()
819 spec->outer_second_cfi = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_cfi, clr); in dr_ste_copy_mask_misc()
[all …]
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| /linux-6.12.1/include/trace/events/ |
| D | thp.h | 40 TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set),
41 TP_ARGS(addr, pte, clr, set),
45 __field(unsigned long, clr)
52 __entry->clr = clr;
57 …and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, __entry->clr, __entry->set)
61 TP_PROTO(unsigned long addr, unsigned long pmd, unsigned long clr, unsigned long set),
62 TP_ARGS(addr, pmd, clr, set)
66 TP_PROTO(unsigned long addr, unsigned long pud, unsigned long clr, unsigned long set),
67 TP_ARGS(addr, pud, clr, set)
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| /linux-6.12.1/arch/arm64/kvm/hyp/nvhe/ |
| D | timer-sr.c | 42 u64 clr = 0, set = 0; in __timer_enable_traps() local
49 clr = CNTHCTL_EL1PCEN; in __timer_enable_traps()
54 clr |= CNTHCTL_EL1PCTEN; in __timer_enable_traps()
57 clr <<= 10; in __timer_enable_traps()
61 sysreg_clear_set(cnthctl_el2, clr, set); in __timer_enable_traps()
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| /linux-6.12.1/arch/powerpc/include/asm/nohash/32/ |
| D | pte-8xx.h | 123 unsigned long clr, unsigned long set, int huge);
135 unsigned long clr = ~pte_val(entry) & _PAGE_RO; in __ptep_set_access_flags() local
138 pte_update(vma->vm_mm, address, ptep, clr, set, huge); in __ptep_set_access_flags()
188 unsigned long clr, unsigned long set, int huge) in __pte_update() argument
192 pte_basic_t new = (old & ~(pte_basic_t)clr) | set; in __pte_update()
211 unsigned long clr, unsigned long set, int huge) in pte_update() argument
218 old = __pte_update(mm, addr, pte_offset_kernel(pmdp, 0), clr, set, huge); in pte_update()
219 __pte_update(mm, addr, pte_offset_kernel(pmdp + 1, 0), clr, set, huge); in pte_update()
221 old = __pte_update(mm, addr, ptep, clr, set, huge); in pte_update()
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| /linux-6.12.1/arch/sparc/lib/ |
| D | ffs.S | 14 clr %o0
21 clr %o1 /* 2 */
25 1: clr %o2
31 clr %o3
34 clr %o4
40 clr %o5
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| /linux-6.12.1/arch/arm64/include/asm/ |
| D | kvm_emulate.h | 550 #define __cpacr_to_cptr_clr(clr, set) \ argument
560 if ((clr) & CPACR_ELx_TTA) \
562 if ((clr) & CPTR_EL2_TAM) \
564 if ((clr) & CPTR_EL2_TCPAC) \
570 #define __cpacr_to_cptr_set(clr, set) \ argument
574 if ((clr) & CPACR_ELx_FPEN) \
576 if ((clr) & CPACR_ELx_ZEN) \
578 if ((clr) & CPACR_ELx_SMEN) \
590 #define cpacr_clear_set(clr, set) \ argument
593 BUILD_BUG_ON((clr) & CPACR_ELx_E0POE); \
[all …]
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| /linux-6.12.1/arch/arm/mach-rpc/ |
| D | irq.c | 168 unsigned int irq, clr, set; in rpc_init_irq() local
181 clr = IRQ_NOREQUEST; in rpc_init_irq()
185 clr |= IRQ_NOPROBE; in rpc_init_irq()
195 irq_modify_status(irq, clr, set); in rpc_init_irq()
203 irq_modify_status(irq, clr, set); in rpc_init_irq()
211 irq_modify_status(irq, clr, set); in rpc_init_irq()
218 irq_modify_status(irq, clr, set); in rpc_init_irq()
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| /linux-6.12.1/drivers/clocksource/ |
| D | timer-armada-370-xp.c | 88 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument
90 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
173 u32 clr = 0, set = 0; in armada_370_xp_timer_starting_cpu() local
178 clr = TIMER0_25MHZ; in armada_370_xp_timer_starting_cpu()
179 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_starting_cpu()
242 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local
261 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init()
264 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
265 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
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| /linux-6.12.1/arch/m68k/ifpsp060/src/ |
| D | itest.S | 81 clr.l TESTCTR(%a6)
91 clr.l TESTCTR(%a6)
101 clr.l TESTCTR(%a6)
111 clr.l TESTCTR(%a6)
121 clr.l TESTCTR(%a6)
132 clr.l TESTCTR(%a6)
142 clr.l TESTCTR(%a6)
169 clr.l %d1
181 clr.l IREGS+0x8(%a6)
182 clr.l IREGS+0xc(%a6)
[all …]
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| D | ilsp.S | 298 clr.l %d1
313 clr.w %d5
327 clr.l DDNORMAL(%a6) # count of shifts for normalization
328 clr.b DDSECOND(%a6) # clear flag for quotient digits
329 clr.l %d1 # %d1 will hold trial quotient
362 clr.w %d6 # word u3 left
405 clr.l %d2
408 clr.w %d3 # %d3 now ls word of divisor
412 clr.w %d3 # %d3 now ms word of divisor
421 clr.l %d1
[all …]
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| /linux-6.12.1/arch/m68k/ifpsp060/ |
| D | os.S | 94 clr.l %d1 | return success
101 clr.l %d1 | return success
127 clr.l %d1 | return success
134 clr.l %d1 | return success
151 clr.l %d0 | clear whole longword
152 clr.l %d1 | assume success
187 clr.l %d1 | assume success
188 clr.l %d0 | clear whole longword
223 clr.l %d1 | assume success
245 clr.l %d1 | assume success
[all …]
|
| /linux-6.12.1/arch/powerpc/include/asm/ |
| D | dcr-native.h | 112 unsigned clr, unsigned set) in __dcri_clrset() argument
120 val = (mfdcrx(base_data) & ~clr) | set; in __dcri_clrset()
124 val = (__mfdcr(base_data) & ~clr) | set; in __dcri_clrset()
138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ argument
140 reg, clr, set)
|
| D | code-patching.h | 131 static inline int modify_instruction(unsigned int *addr, unsigned int clr, in modify_instruction() argument
134 return patch_instruction(addr, ppc_inst((*addr & ~clr) | set)); in modify_instruction()
137 static inline int modify_instruction_site(s32 *site, unsigned int clr, unsigned int set) in modify_instruction_site() argument
139 return modify_instruction((unsigned int *)patch_site_addr(site), clr, set); in modify_instruction_site()
|
| /linux-6.12.1/drivers/net/wireless/ath/ath9k/ |
| D | ar9003_wow.c | 127 u32 set, clr; in ath9k_hw_wow_apply_pattern() local
160 clr = AR_WOW_LENGTH1_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern()
165 clr = AR_WOW_LENGTH2_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern()
170 clr = AR_WOW_LENGTH3_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); in ath9k_hw_wow_apply_pattern()
175 clr = AR_WOW_LENGTH4_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr); in ath9k_hw_wow_apply_pattern()
|
| /linux-6.12.1/arch/m68k/math-emu/ |
| D | fp_util.S | 70 2: clr.l %d0
99 clr.l %d1 | sign defaults to zero
109 clr.l (%a0)
116 clr.l (%a0)+
117 clr.l (%a0)+
118 clr.l (%a0)
142 clr.l (%a0) | low lword = 0
|
| /linux-6.12.1/kernel/irq/ |
| D | devres.c | 237 unsigned int clr; member
245 irq_remove_generic_chip(this->gc, this->msk, this->clr, this->set); in devm_irq_remove_generic_chip()
265 unsigned int clr, unsigned int set) in devm_irq_setup_generic_chip() argument
274 irq_setup_generic_chip(gc, msk, flags, clr, set); in devm_irq_setup_generic_chip()
278 dr->clr = clr; in devm_irq_setup_generic_chip()
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| /linux-6.12.1/arch/powerpc/include/asm/book3s/64/ |
| D | radix.h | 154 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr, in __radix_pte_update() argument
166 : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr)) in __radix_pte_update()
174 pte_t *ptep, unsigned long clr, in radix__pte_update() argument
180 old_pte = __radix_pte_update(ptep, clr, set); in radix__pte_update()
286 pmd_t *pmdp, unsigned long clr,
289 pud_t *pudp, unsigned long clr,
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| D | hash.h | 165 static inline unsigned long hash__pte_update_one(pte_t *ptep, unsigned long clr, in hash__pte_update_one() argument
179 : "r" (ptep), "r" (cpu_to_be64(clr)), "m" (*ptep), in hash__pte_update_one()
188 pte_t *ptep, unsigned long clr, in hash__pte_update() argument
194 old = hash__pte_update_one(ptep, clr, set); in hash__pte_update()
210 hash__pte_update_one(ptep + i, clr, set); in hash__pte_update()
|
| /linux-6.12.1/drivers/gpu/drm/nouveau/dispnv50/ |
| D | head.c | 43 union nv50_head_atom_mask clr = { in nv50_head_flush_clr() local
44 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), in nv50_head_flush_clr()
46 if (clr.crc) nv50_crc_atomic_clr(head); in nv50_head_flush_clr()
47 if (clr.olut) head->func->olut_clr(head); in nv50_head_flush_clr()
48 if (clr.core) head->func->core_clr(head); in nv50_head_flush_clr()
49 if (clr.curs) head->func->curs_clr(head); in nv50_head_flush_clr()
412 asyh->clr.core = true; in nv50_head_atomic_check()
420 asyh->clr.curs = true; in nv50_head_atomic_check()
428 asyh->clr.olut = true; in nv50_head_atomic_check()
431 asyh->clr.olut = armh->olut.visible; in nv50_head_atomic_check()
[all …]
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| D | wndw.c | 130 union nv50_wndw_atom_mask clr = { in nv50_wndw_flush_clr() local
131 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), in nv50_wndw_flush_clr()
133 if (clr.sema ) wndw->func-> sema_clr(wndw); in nv50_wndw_flush_clr()
134 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); in nv50_wndw_flush_clr()
135 if (clr.xlut ) wndw->func-> xlut_clr(wndw); in nv50_wndw_flush_clr()
136 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
137 if (clr.image) wndw->func->image_clr(wndw); in nv50_wndw_flush_clr()
413 asyw->clr.xlut = armw->xlut.handle != 0; in nv50_wndw_atomic_check_lut()
428 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
504 asyw->clr.ntfy = armw->ntfy.handle != 0; in nv50_wndw_atomic_check()
[all …]
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| /linux-6.12.1/drivers/gpio/ |
| D | gpio-mmio.c | 490 void __iomem *clr, in bgpio_setup_io() argument
498 if (set && clr) { in bgpio_setup_io()
500 gc->reg_clr = clr; in bgpio_setup_io()
503 } else if (set && !clr) { in bgpio_setup_io()
600 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, in bgpio_init() argument
623 ret = bgpio_setup_io(gc, dat, set, clr, flags); in bgpio_init()
722 void __iomem *clr; in bgpio_pdev_probe() local
754 clr = bgpio_map(pdev, "clr", sz); in bgpio_pdev_probe()
755 if (IS_ERR(clr)) in bgpio_pdev_probe()
756 return PTR_ERR(clr); in bgpio_pdev_probe()
[all …]
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| /linux-6.12.1/drivers/pinctrl/ |
| D | pinctrl-microchip-sgpio.c | 188 u32 clr, set; in sgpio_configure_bitstream() local
192 clr = SGPIO_LUTON_PORT_WIDTH; in sgpio_configure_bitstream()
197 clr = SGPIO_OCELOT_PORT_WIDTH; in sgpio_configure_bitstream()
202 clr = SGPIO_SPARX5_PORT_WIDTH; in sgpio_configure_bitstream()
209 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); in sgpio_configure_bitstream()
214 u32 clr, set; in sgpio_configure_clock() local
218 clr = SGPIO_LUTON_CLK_FREQ; in sgpio_configure_clock()
222 clr = SGPIO_OCELOT_CLK_FREQ; in sgpio_configure_clock()
226 clr = SGPIO_SPARX5_CLK_FREQ; in sgpio_configure_clock()
232 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); in sgpio_configure_clock()
[all …]
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| /linux-6.12.1/arch/mips/include/asm/octeon/ |
| D | cvmx-gpio-defs.h | 296 uint64_t clr:24; member
298 uint64_t clr:24;
305 uint64_t clr:16; member
307 uint64_t clr:16;
314 uint64_t clr:20; member
316 uint64_t clr:20;
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| /linux-6.12.1/drivers/staging/media/omap4iss/ |
| D | iss.h | 191 u32 offset, u32 clr) in iss_reg_clr() argument
195 iss_reg_write(iss, res, offset, v & ~clr); in iss_reg_clr()
226 u32 offset, u32 clr, u32 set) in iss_reg_update() argument
230 iss_reg_write(iss, res, offset, (v & ~clr) | set); in iss_reg_update()
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| /linux-6.12.1/arch/mips/pic32/pic32mzda/ |
| D | config.c | 71 u32 clr, set; in pic32_set_sdhci_adma_fifo_threshold() local
73 clr = (0x3ff << 4) | (0x3ff << 16); in pic32_set_sdhci_adma_fifo_threshold()
75 return pic32_conf_modify_atomic(PIC32_CFGCON2, clr, set); in pic32_set_sdhci_adma_fifo_threshold()
|