Searched refs:bit_group_1 (Results 1 – 3 of 3) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/i915/gt/ |
| D | gen8_engine_cs.h | 54 u32 bit_group_1, u32 offset) in __gen8_emit_pipe_control() argument
59 batch[1] = bit_group_1; in __gen8_emit_pipe_control()
66 u32 bit_group_1, u32 offset) in gen8_emit_pipe_control() argument
68 return __gen8_emit_pipe_control(batch, 0, bit_group_1, offset); in gen8_emit_pipe_control()
72 u32 bit_group_1, u32 offset) in gen12_emit_pipe_control() argument
75 bit_group_1, offset); in gen12_emit_pipe_control()
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| D | gen8_engine_cs.c | 254 u32 bit_group_1 = 0; in gen12_emit_flush_rcs() local
280 bit_group_1 |= PIPE_CONTROL_FLUSH_L3; in gen12_emit_flush_rcs()
282 bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; in gen12_emit_flush_rcs()
283 bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; in gen12_emit_flush_rcs()
284 bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; in gen12_emit_flush_rcs()
286 bit_group_1 |= PIPE_CONTROL_DEPTH_STALL; in gen12_emit_flush_rcs()
287 bit_group_1 |= PIPE_CONTROL_DC_FLUSH_ENABLE; in gen12_emit_flush_rcs()
288 bit_group_1 |= PIPE_CONTROL_FLUSH_ENABLE; in gen12_emit_flush_rcs()
290 bit_group_1 |= PIPE_CONTROL_STORE_DATA_INDEX; in gen12_emit_flush_rcs()
291 bit_group_1 |= PIPE_CONTROL_QW_WRITE; in gen12_emit_flush_rcs()
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| /linux-6.12.1/drivers/gpu/drm/xe/ |
| D | xe_ring_ops.c | 129 emit_pipe_control(u32 *dw, int i, u32 bit_group_0, u32 bit_group_1, u32 offset, u32 value) in emit_pipe_control() argument
132 dw[i++] = bit_group_1; in emit_pipe_control()
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