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Searched refs:asyw (Results 1 – 18 of 18) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/nouveau/dispnv50/
Dwndw.c115 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in nv50_wndw_wait_armed() argument
118 if (asyw->set.ntfy) { in nv50_wndw_wait_armed()
120 asyw->ntfy.offset, in nv50_wndw_wait_armed()
128 struct nv50_wndw_atom *asyw) in nv50_wndw_flush_clr() argument
131 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), in nv50_wndw_flush_clr()
144 struct nv50_wndw_atom *asyw) in nv50_wndw_flush_set() argument
147 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING; in nv50_wndw_flush_set()
148 asyw->image.interval = 1; in nv50_wndw_flush_set()
151 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); in nv50_wndw_flush_set()
152 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); in nv50_wndw_flush_set()
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Dwndwc37e.c40 wndwc37e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in wndwc37e_csc_set() argument
48 PUSH_MTHD(push, NVC37E, SET_CSC_RED2RED, asyw->csc.matrix, 12); in wndwc37e_csc_set()
66 wndwc37e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in wndwc37e_ilut_set() argument
75 NVVAL(NVC37E, SET_CONTROL_INPUT_LUT, OUTPUT_MODE, asyw->xlut.i.output_mode) | in wndwc37e_ilut_set()
76 NVVAL(NVC37E, SET_CONTROL_INPUT_LUT, RANGE, asyw->xlut.i.range) | in wndwc37e_ilut_set()
77 NVVAL(NVC37E, SET_CONTROL_INPUT_LUT, SIZE, asyw->xlut.i.size), in wndwc37e_ilut_set()
79 SET_OFFSET_INPUT_LUT, asyw->xlut.i.offset >> 8, in wndwc37e_ilut_set()
80 SET_CONTEXT_DMA_INPUT_LUT, asyw->xlut.handle); in wndwc37e_ilut_set()
85 wndwc37e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size) in wndwc37e_ilut() argument
87 asyw->xlut.i.size = size == 1024 ? NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025 : in wndwc37e_ilut()
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Dwndwc57e.c33 wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in wndwc57e_image_set() argument
42 NVVAL(NVC57E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) | in wndwc57e_image_set()
43 NVVAL(NVC57E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | in wndwc57e_image_set()
47 NVVAL(NVC57E, SET_SIZE, WIDTH, asyw->image.w) | in wndwc57e_image_set()
48 NVVAL(NVC57E, SET_SIZE, HEIGHT, asyw->image.h), in wndwc57e_image_set()
51 NVVAL(NVC57E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | in wndwc57e_image_set()
52 NVVAL(NVC57E, SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), in wndwc57e_image_set()
55 NVVAL(NVC57E, SET_PARAMS, FORMAT, asyw->image.format) | in wndwc57e_image_set()
61 NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) | in wndwc57e_image_set()
62 NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6)); in wndwc57e_image_set()
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Dbase907c.c29 base907c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in base907c_image_set() argument
38 NVVAL(NV907C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | in base907c_image_set()
40 NVVAL(NV907C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); in base907c_image_set()
42 PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1); in base907c_image_set()
44 PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8, in base907c_image_set()
48 NVVAL(NV907C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | in base907c_image_set()
49 NVVAL(NV907C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), in base907c_image_set()
52 NVVAL(NV907C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | in base907c_image_set()
53 NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) | in base907c_image_set()
54 NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) | in base907c_image_set()
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Dcurs507a.c59 curs507a_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in curs507a_point() argument
65 NVVAL(NV507A, SET_CURSOR_HOT_SPOT_POINT_OUT, X, asyw->point.x) | in curs507a_point()
66 NVVAL(NV507A, SET_CURSOR_HOT_SPOT_POINT_OUT, Y, asyw->point.y)); in curs507a_point()
79 struct nv50_wndw_atom *asyw) in curs507a_prepare() argument
82 u32 offset = asyw->image.offset[0]; in curs507a_prepare()
91 curs507a_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, in curs507a_release() argument
98 curs507a_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, in curs507a_acquire() argument
102 struct nv50_head *head = nv50_head(asyw->state.crtc); in curs507a_acquire()
103 struct drm_framebuffer *fb = asyw->state.fb; in curs507a_acquire()
106 ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state, in curs507a_acquire()
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Dovly507e.c34 ovly507e_scale_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in ovly507e_scale_set() argument
43 NVVAL(NV507E, SET_POINT_IN, X, asyw->scale.sx) | in ovly507e_scale_set()
44 NVVAL(NV507E, SET_POINT_IN, Y, asyw->scale.sy), in ovly507e_scale_set()
47 NVVAL(NV507E, SET_SIZE_IN, WIDTH, asyw->scale.sw) | in ovly507e_scale_set()
48 NVVAL(NV507E, SET_SIZE_IN, HEIGHT, asyw->scale.sh), in ovly507e_scale_set()
51 NVVAL(NV507E, SET_SIZE_OUT, WIDTH, asyw->scale.dw)); in ovly507e_scale_set()
56 ovly507e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in ovly507e_image_set() argument
66 NVVAL(NV507E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); in ovly507e_image_set()
68 PUSH_MTHD(push, NV507E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); in ovly507e_image_set()
73 PUSH_MTHD(push, NV507E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8); in ovly507e_image_set()
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Dbase507c.c66 base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in base507c_image_set() argument
75 NVVAL(NV507C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | in base507c_image_set()
76 NVVAL(NV507C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); in base507c_image_set()
78 PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); in base507c_image_set()
80 if (asyw->image.format == NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16) { in base507c_image_set()
96 PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8); in base507c_image_set()
99 NVVAL(NV507C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | in base507c_image_set()
100 NVVAL(NV507C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), in base507c_image_set()
103 NVVAL(NV507C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout) | in base507c_image_set()
104 NVVAL(NV507C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) | in base507c_image_set()
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Dwndwc67e.c30 wndwc67e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in wndwc67e_image_set() argument
39 NVVAL(NVC57E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) | in wndwc67e_image_set()
40 NVVAL(NVC57E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | in wndwc67e_image_set()
44 NVVAL(NVC57E, SET_SIZE, WIDTH, asyw->image.w) | in wndwc67e_image_set()
45 NVVAL(NVC57E, SET_SIZE, HEIGHT, asyw->image.h), in wndwc67e_image_set()
48 NVVAL(NVC57E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh), in wndwc67e_image_set()
51 NVVAL(NVC57E, SET_PARAMS, FORMAT, asyw->image.format) | in wndwc67e_image_set()
57 NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) | in wndwc67e_image_set()
58 NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6)); in wndwc67e_image_set()
60 PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1); in wndwc67e_image_set()
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Dovly907e.c30 ovly907e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in ovly907e_image_set() argument
40 NVVAL(NV907E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); in ovly907e_image_set()
42 PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); in ovly907e_image_set()
47 PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8); in ovly907e_image_set()
50 NVVAL(NV907E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | in ovly907e_image_set()
51 NVVAL(NV907E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), in ovly907e_image_set()
54 NVVAL(NV907E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | in ovly907e_image_set()
55 NVVAL(NV907E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) | in ovly907e_image_set()
56 NVVAL(NV907E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) | in ovly907e_image_set()
57 NVVAL(NV907E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), in ovly907e_image_set()
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Dbase827c.c29 base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in base827c_image_set() argument
38 NVVAL(NV827C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | in base827c_image_set()
39 NVVAL(NV827C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); in base827c_image_set()
41 PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1); in base827c_image_set()
43 if (asyw->image.format == NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16) { in base827c_image_set()
59 PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8, in base827c_image_set()
63 NVVAL(NV827C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | in base827c_image_set()
64 NVVAL(NV827C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), in base827c_image_set()
67 NVVAL(NV827C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | in base827c_image_set()
68 NVVAL(NV827C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) | in base827c_image_set()
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Dovly827e.c33 ovly827e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in ovly827e_image_set() argument
43 NVVAL(NV827E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); in ovly827e_image_set()
45 PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); in ovly827e_image_set()
50 PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8); in ovly827e_image_set()
53 NVVAL(NV827E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | in ovly827e_image_set()
54 NVVAL(NV827E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), in ovly827e_image_set()
57 NVVAL(NV827E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | in ovly827e_image_set()
58 NVVAL(NV827E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) | in ovly827e_image_set()
59 NVVAL(NV827E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) | in ovly827e_image_set()
60 NVVAL(NV827E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), in ovly827e_image_set()
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Dcursc37a.c38 cursc37a_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in cursc37a_point() argument
44 NVVAL(NVC37A, SET_CURSOR_HOT_SPOT_POINT_OUT, X, asyw->point.x) | in cursc37a_point()
45 NVVAL(NVC37A, SET_CURSOR_HOT_SPOT_POINT_OUT, Y, asyw->point.y)); in cursc37a_point()
Dwimmc37b.c47 wimmc37b_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) in wimmc37b_point() argument
56 NVVAL(NVC37B, SET_POINT_OUT, X, asyw->point.x) | in wimmc37b_point()
57 NVVAL(NVC37B, SET_POINT_OUT, Y, asyw->point.y)); in wimmc37b_point()
Dwndw.h49 int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
51 void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
54 struct nv50_wndw_atom *asyw);
Dhead917d.c103 head917d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw, in head917d_curs_layout() argument
106 switch (asyw->state.fb->width) { in head917d_curs_layout()
Dhead507d.c163 head507d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw, in head507d_curs_format() argument
166 switch (asyw->image.format) { in head507d_curs_format()
176 head507d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw, in head507d_curs_layout() argument
179 switch (asyw->image.w) { in head507d_curs_layout()
Ddisp.c2210 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); in nv50_disp_atomic_commit_tail() local
2214 asyw->clr.mask, asyw->set.mask); in nv50_disp_atomic_commit_tail()
2215 if (!asyw->clr.mask) in nv50_disp_atomic_commit_tail()
2218 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); in nv50_disp_atomic_commit_tail()
2339 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); in nv50_disp_atomic_commit_tail() local
2343 asyw->set.mask, asyw->clr.mask); in nv50_disp_atomic_commit_tail()
2344 if ( !asyw->set.mask && in nv50_disp_atomic_commit_tail()
2345 (!asyw->clr.mask || atom->flush_disable)) in nv50_disp_atomic_commit_tail()
2348 nv50_wndw_flush_set(wndw, interlock, asyw); in nv50_disp_atomic_commit_tail()
2374 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); in nv50_disp_atomic_commit_tail() local
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Dheadc37d.c154 headc37d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw, in headc37d_curs_format() argument
157 asyh->curs.format = asyw->image.format; in headc37d_curs_format()