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Searched refs:UVD_RB_ARB_CTRL__VCPU_DIS_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dvcn_v5_0_0.c820 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v5_0_0_start()
986 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, in vcn_v5_0_0_stop()
987 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v5_0_0_stop()
Dvcn_v4_0_5.c1088 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v4_0_5_start()
1252 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, in vcn_v4_0_5_stop()
1253 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v4_0_5_stop()
Dvcn_v4_0_3.c1176 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v4_0_3_start()
1342 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, in vcn_v4_0_3_stop()
1343 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v4_0_3_stop()
Dvcn_v4_0.c1176 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v4_0_start()
1589 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, in vcn_v4_0_stop()
1590 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v4_0_stop()
Dvcn_v2_5.c1108 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v2_5_start()
1467 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, in vcn_v2_5_stop()
1468 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v2_5_stop()
Dvcn_v3_0.c1227 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v3_0_start()
1607 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, in vcn_v3_0_stop()
1608 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); in vcn_v3_0_stop()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h2543 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_2_0_0_sh_mask.h1769 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_2_6_0_sh_mask.h4371 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_3_0_0_sh_mask.h3483 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_5_0_0_sh_mask.h2935 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_4_0_5_sh_mask.h3339 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_4_0_0_sh_mask.h3378 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro
Dvcn_4_0_3_sh_mask.h3408 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK … macro