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Searched refs:UVD_MPC_SET_MUXA1__VARA_5_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h612 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
Duvd_3_1_sh_mask.h487 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f macro
Duvd_4_0_sh_mask.h504 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003fL macro
Duvd_4_2_sh_mask.h491 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f macro
Duvd_5_0_sh_mask.h523 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f macro
Duvd_6_0_sh_mask.h525 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1119 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
Dvcn_2_5_sh_mask.h2860 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
Dvcn_2_0_0_sh_mask.h2625 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
Dvcn_2_6_0_sh_mask.h2852 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
Dvcn_3_0_0_sh_mask.h3933 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
Dvcn_4_0_5_sh_mask.h4050 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
Dvcn_4_0_0_sh_mask.h4183 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
Dvcn_4_0_3_sh_mask.h4226 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro