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Searched refs:UVD_HWIP (Results 1 – 20 of 20) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_discovery.c217 [UVD_HWIP] = UVD_HWID,
357 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && in amdgpu_discovery_harvest_config_quirk()
2244 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in amdgpu_discovery_set_mm_ip_blocks()
2254 amdgpu_ip_version(adev, UVD_HWIP, 0)); in amdgpu_discovery_set_mm_ip_blocks()
2271 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in amdgpu_discovery_set_mm_ip_blocks()
2327 amdgpu_ip_version(adev, UVD_HWIP, 0)); in amdgpu_discovery_set_mm_ip_blocks()
2448 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2470 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2493 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); in amdgpu_discovery_set_ip_blocks()
2509 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); in amdgpu_discovery_set_ip_blocks()
[all …]
Damdgpu_vcn.c99 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix)); in amdgpu_vcn_early_init()
101 if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6)) in amdgpu_vcn_early_init()
139 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) { in amdgpu_vcn_sw_init()
152 amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0); in amdgpu_vcn_sw_init()
188 if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) { in amdgpu_vcn_sw_init()
191 } else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) { in amdgpu_vcn_sw_init()
1022 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) { in amdgpu_vcn_unified_ring_test_ib()
1072 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == in amdgpu_vcn_setup_ucode()
Darct_reg_init.c41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in arct_reg_base_init()
Dvega10_reg_init.c41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
Dvega20_reg_init.c41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
Djpeg_v4_0_5.c72 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in jpeg_v4_0_5_early_init()
82 amdgpu_ip_version(adev, UVD_HWIP, 0)); in jpeg_v4_0_5_early_init()
Damdgpu_ucode.c1298 } else if (block_type == UVD_HWIP) { in amdgpu_ucode_legacy_naming()
1299 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in amdgpu_ucode_legacy_naming()
1412 case UVD_HWIP: in amdgpu_ucode_ip_version_decode()
Dvcn_v3_0.c139 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == in vcn_v3_0_early_init()
269 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2)) in vcn_v3_0_sw_init()
271 else if (amdgpu_ip_version(adev, UVD_HWIP, 0) == in vcn_v3_0_sw_init()
1303 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != in vcn_v3_0_start()
1677 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != in vcn_v3_0_pause_dpg_mode()
Djpeg_v3_0.c55 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in jpeg_v3_0_early_init()
Damdgpu_dev_coredump.c54 [UVD_HWIP] = "UVD/JPEG/VCN",
Dsoc24.c80 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc24_query_video_codecs()
Damdgpu.h710 UVD_HWIP, enumerator
711 VCN_HWIP = UVD_HWIP,
Djpeg_v2_5.c131 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0)) in jpeg_v2_5_sw_init()
Dvcn_v2_5.c229 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0)) in vcn_v2_5_sw_init()
249 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == in vcn_v2_5_sw_init()
845 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(2, 6, 0)) in vcn_v2_6_enable_ras()
Duvd_v7_0.c1302 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; in uvd_v7_0_ring_patch_cs_in_place()
1303 reg += p->adev->reg_offset[UVD_HWIP][1][1]; in uvd_v7_0_ring_patch_cs_in_place()
Dsoc21.c156 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc21_query_video_codecs()
Dnv.c216 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in nv_query_video_codecs()
Damdgpu_uvd.c1142 offset = adev->reg_offset[UVD_HWIP][ring->me][1]; in amdgpu_uvd_send_msg()
Dsoc15.c190 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc15_query_video_codecs()
Damdgpu_kms.c523 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); in amdgpu_hw_ip_info()