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Searched refs:UVD_CGC_GATE__REGS_MASK (Results 1 – 24 of 24) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h400 #define UVD_CGC_GATE__REGS_MASK … macro
Duvd_3_1_sh_mask.h129 #define UVD_CGC_GATE__REGS_MASK 0x8 macro
Duvd_4_0_sh_mask.h96 #define UVD_CGC_GATE__REGS_MASK 0x00000008L macro
Duvd_4_2_sh_mask.h129 #define UVD_CGC_GATE__REGS_MASK 0x8 macro
Duvd_5_0_sh_mask.h141 #define UVD_CGC_GATE__REGS_MASK 0x8 macro
Duvd_6_0_sh_mask.h143 #define UVD_CGC_GATE__REGS_MASK 0x8 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h828 #define UVD_CGC_GATE__REGS_MASK … macro
Dvcn_2_5_sh_mask.h1898 #define UVD_CGC_GATE__REGS_MASK … macro
Dvcn_2_0_0_sh_mask.h1847 #define UVD_CGC_GATE__REGS_MASK … macro
Dvcn_2_6_0_sh_mask.h3569 #define UVD_CGC_GATE__REGS_MASK … macro
Dvcn_3_0_0_sh_mask.h2628 #define UVD_CGC_GATE__REGS_MASK … macro
Dvcn_5_0_0_sh_mask.h63 #define UVD_CGC_GATE__REGS_MASK … macro
Dvcn_4_0_5_sh_mask.h59 #define UVD_CGC_GATE__REGS_MASK … macro
Dvcn_4_0_0_sh_mask.h63 #define UVD_CGC_GATE__REGS_MASK … macro
Dvcn_4_0_3_sh_mask.h63 #define UVD_CGC_GATE__REGS_MASK … macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c669 data3 &= ~UVD_CGC_GATE__REGS_MASK; in uvd_v5_0_enable_clock_gating()
Duvd_v6_0.c1328 data3 &= ~UVD_CGC_GATE__REGS_MASK; in uvd_v6_0_enable_clock_gating()
Dvcn_v4_0_5.c663 | UVD_CGC_GATE__REGS_MASK in vcn_v4_0_5_disable_clock_gating()
Dvcn_v4_0_3.c585 | UVD_CGC_GATE__REGS_MASK in vcn_v4_0_3_disable_clock_gating()
Dvcn_v1_0.c527 | UVD_CGC_GATE__REGS_MASK in vcn_v1_0_disable_clock_gating()
Dvcn_v2_0.c555 | UVD_CGC_GATE__REGS_MASK in vcn_v2_0_disable_clock_gating()
Dvcn_v4_0.c727 | UVD_CGC_GATE__REGS_MASK in vcn_v4_0_disable_clock_gating()
Dvcn_v2_5.c642 | UVD_CGC_GATE__REGS_MASK in vcn_v2_5_disable_clock_gating()
Dvcn_v3_0.c761 | UVD_CGC_GATE__REGS_MASK in vcn_v3_0_disable_clock_gating()