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Searched refs:UVD_CGC_CTRL (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c693 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | in uvd_v5_0_set_sw_clock_gating()
694 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); in uvd_v5_0_set_sw_clock_gating()
Duvd_v6_0.c1350 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | in uvd_v6_0_set_sw_clock_gating()
1351 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); in uvd_v6_0_set_sw_clock_gating()
Duvd_v7_0.c1632 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1633 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
Dsid.h1630 #define UVD_CGC_CTRL 0x3dc2 macro
/linux-6.12.1/drivers/gpu/drm/radeon/
Dsi.c5156 tmp = RREG32(UVD_CGC_CTRL); in si_set_uvd_dcm()
5168 WREG32(UVD_CGC_CTRL, tmp); in si_set_uvd_dcm()
5179 u32 tmp = RREG32(UVD_CGC_CTRL); in si_init_uvd_internal_cg()
5181 WREG32(UVD_CGC_CTRL, tmp); in si_init_uvd_internal_cg()
5441 orig = data = RREG32(UVD_CGC_CTRL); in si_enable_uvd_mgcg()
5444 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
5453 orig = data = RREG32(UVD_CGC_CTRL); in si_enable_uvd_mgcg()
5456 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
Dsid.h1568 #define UVD_CGC_CTRL 0xF4B0 macro
Dcikd.h2085 #define UVD_CGC_CTRL 0xF4B0 macro
Dcik.c6212 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6215 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6221 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6224 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()