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Searched refs:SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_sh_mask.h1473 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
Dsdma1_4_2_sh_mask.h1479 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
Dsdma1_4_2_2_sh_mask.h1487 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_0_sh_mask.h1662 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
Doss_2_4_sh_mask.h1862 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
Doss_3_0_1_sh_mask.h2808 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
Doss_3_0_sh_mask.h2922 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/sdma/
Dsdma_4_4_0_sh_mask.h4089 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_sh_mask.h4037 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
Dgc_10_3_0_sh_mask.h4210 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro