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Searched refs:SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_sh_mask.h546 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro
Dsdma0_4_0_sh_mask.h547 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 macro
Dsdma0_4_2_sh_mask.h547 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro
Dsdma0_4_2_2_sh_mask.h553 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_0_sh_mask.h970 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 macro
Doss_2_4_sh_mask.h1054 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 macro
Doss_3_0_1_sh_mask.h1072 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 macro
Doss_3_0_sh_mask.h1578 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/sdma/
Dsdma_4_4_0_sh_mask.h238 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_sh_mask.h234 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro
Dgc_11_0_0_sh_mask.h223 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro
Dgc_12_0_0_sh_mask.h200 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro
Dgc_11_0_3_sh_mask.h233 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro
Dgc_10_1_0_sh_mask.h255 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro
Dgc_10_3_0_sh_mask.h256 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT … macro