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Searched refs:SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_sh_mask.h548 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro
Dsdma0_4_0_sh_mask.h549 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 macro
Dsdma0_4_2_sh_mask.h549 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro
Dsdma0_4_2_2_sh_mask.h555 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_0_sh_mask.h974 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 macro
Doss_2_4_sh_mask.h1058 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 macro
Doss_3_0_1_sh_mask.h1076 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 macro
Doss_3_0_sh_mask.h1582 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/sdma/
Dsdma_4_4_0_sh_mask.h240 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_sh_mask.h236 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro
Dgc_11_0_0_sh_mask.h225 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro
Dgc_12_0_0_sh_mask.h202 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro
Dgc_11_0_3_sh_mask.h235 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro
Dgc_10_1_0_sh_mask.h257 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro
Dgc_10_3_0_sh_mask.h258 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT … macro