Searched refs:SDMA0_ME_CNTL (Results 1 – 3 of 3) sorted by relevance
345 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); in cik_sdma_enable()350 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); in cik_sdma_enable()
4954 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()4956 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()4960 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()4962 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()5157 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()5159 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()5161 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()5163 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
1977 #define SDMA0_ME_CNTL 0xD048 macro