Home
last modified time | relevance | path

Searched refs:SDMA0_CNTL (Results 1 – 12 of 12) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dsdma_v3_0.c579 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
581 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
590 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
1336 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1341 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1352 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1357 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
Dsdma_v2_4.c1000 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1005 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1016 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1021 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
Dsdma_v5_2.c489 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_2_ctx_switch_enable()
630 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v5_2_gfx_resume()
633 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); in sdma_v5_2_gfx_resume()
1457 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_2_set_trap_irq_state()
Dsdma_v5_0.c661 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_0_ctx_switch_enable()
816 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v5_0_gfx_resume()
819 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); in sdma_v5_0_gfx_resume()
1595 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_0_set_trap_irq_state()
Dcik_sdma.c372 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
381 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
Dsdma_v4_0.c1012 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v4_0_ctx_switch_enable()
1415 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v4_0_start()
2067 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
Dsdma_v6_0.c436 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v6_0_ctxempty_int_enable()
1483 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v6_0_set_trap_irq_state()
Dsdma_v7_0.c1472 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v7_0_set_trap_irq_state()
/linux-6.12.1/drivers/gpu/drm/radeon/
Dcik_reg.h204 #define SDMA0_CNTL 0xD010 macro
Dcik_sdma.c313 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable()
318 WREG32(SDMA0_CNTL + reg_offset, value); in cik_sdma_ctx_switch_enable()
Dcik.c6863 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6864 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
6865 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6866 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
7048 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7049 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7219 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); in cik_irq_set()
7220 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()
Dcikd.h1960 #define SDMA0_CNTL 0xD010 macro