/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | sdma_v4_4.c | 60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 88 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 92 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), 96 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER), [all …]
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D | sdma_v4_0.c | 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), [all …]
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D | amdgpu_amdkfd_gfx_v10_3.c | 143 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 147 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 151 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
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D | sdma_v4_4_2.c | 112 u32 dev_inst = GET_INST(SDMA0, instance); in sdma_v4_4_2_get_reg_offset() 1850 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); in sdma_v4_4_2_get_clockgating_state() 1855 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); in sdma_v4_4_2_get_clockgating_state() 1997 dev_inst = GET_INST(SDMA0, i); in sdma_v4_4_2_set_ring_funcs() 2193 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2229 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_query_ras_error_count() 2267 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_reset_ras_error_count()
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D | amdgpu_amdkfd_gc_9_4_3.c | 48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
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D | amdgpu_amdkfd_gfx_v12.c | 85 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
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D | amdgpu_amdkfd_arcturus.c | 81 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
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D | soc24.c | 121 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
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D | nbio_v7_9.c | 83 dev_inst = GET_INST(SDMA0, instance); in nbio_v7_9_sdma_doorbell_range()
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D | amdgpu_amdkfd_gfx_v11.c | 134 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
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D | soc21.c | 263 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
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D | nv.c | 342 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
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D | amdgpu_amdkfd_gfx_v10.c | 165 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
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D | sdma_v2_4.c | 278 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
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D | amdgpu_amdkfd_gfx_v9.c | 194 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
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D | soc15.c | 365 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
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D | sdma_v3_0.c | 454 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
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D | amdgpu_psp.c | 1843 dev_mask = GET_MASK(SDMA0, instance_mask); in psp_ras_trigger_error()
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/linux-6.12.1/drivers/gpu/drm/radeon/ |
D | cik_sdma.c | 177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
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D | cikd.h | 860 #define SDMA0 (1 << 10) macro
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