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Searched refs:RLC_LB_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/radeon/
Dsid.h1304 #define RLC_LB_CNTL 0xC30C macro
Dcikd.h1403 #define RLC_LB_CNTL 0xC364 macro
Dsi.c5832 tmp = RREG32(RLC_LB_CNTL); in si_enable_lbpw()
5837 WREG32(RLC_LB_CNTL, tmp); in si_enable_lbpw()
5862 WREG32(RLC_LB_CNTL, 0); in si_rlc_resume()
Dcik.c5773 tmp = RREG32(RLC_LB_CNTL); in cik_enable_lbpw()
5778 WREG32(RLC_LB_CNTL, tmp); in cik_enable_lbpw()
5934 WREG32(RLC_LB_CNTL, 0x80000004); in cik_rlc_resume()
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c1739 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); in gfx_v9_0_init_lbpw()
1740 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); in gfx_v9_0_init_lbpw()
1788 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); in gfx_v9_4_init_lbpw()
1789 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); in gfx_v9_4_init_lbpw()
1798 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_lbpw()
Dsid.h1332 #define RLC_LB_CNTL 0x30C3 macro
Dgfx_v6_0.c2390 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()