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Searched refs:RING_START (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_ring_submission.c223 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
270 ENGINE_READ(engine, RING_START), in xcs_resume()
338 ENGINE_READ_FW(engine, RING_START)); in reset_prepare()
347 ENGINE_READ_FW(engine, RING_START)); in reset_prepare()
Dintel_engine_regs.h18 #define RING_START(base) _MMIO((base) + 0x38) macro
Dselftest_lrc.c304 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
444 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base)); in __live_lrc_state()
1588 *cs++ = i915_mmio_reg_offset(RING_START(0)); in emit_wabb_ctx_canary()
Dintel_gt.c149 intel_uncore_write(uncore, RING_START(base), 0); in init_unused_ring()
Dintel_engine_cs.c2093 ENGINE_READ(engine, RING_START)); in intel_engine_print_registers()
Dintel_execlists_submission.c1976 ENGINE_READ(engine, RING_START), in process_csb()
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_engine_regs.h52 #define RING_START(base) XE_REG((base) + 0x38) macro
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_hw_engine.c936 snapshot->reg.ring_start = xe_hw_engine_mmio_read32(hwe, RING_START(0)); in xe_hw_engine_snapshot_capture()
/linux-6.12.1/drivers/gpu/drm/i915/
Di915_request.c2236 u32 ring = ENGINE_READ(engine, RING_START); in engine_match_ring()
Dintel_gvt_mmio_table.c88 MMIO_RING_D(RING_START); in iterate_generic_mmio()
Di915_gpu_error.c1297 ee->start = ENGINE_READ(engine, RING_START); in engine_record_registers()
/linux-6.12.1/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_capture.c67 { RING_START(0), 0, 0, "START" }, \
/linux-6.12.1/drivers/gpu/drm/i915/gvt/
Dscheduler.c652 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) = in update_vreg_in_ctx()
Dhandlers.c2226 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); in init_generic_mmio_info()