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Searched refs:OTG_V_TOTAL (Results 1 – 20 of 20) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddcn30_fpu.c211 REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min); in optc3_fpu_set_vrr_m_const()
231 REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, in optc3_fpu_set_vrr_m_const()
251 REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min); in optc3_fpu_set_vrr_m_const()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn10/
Ddcn10_optc.c223 REG_SET(OTG_V_TOTAL, 0, in optc1_program_timing()
224 OTG_V_TOTAL, v_total); in optc1_program_timing()
1345 REG_GET(OTG_V_TOTAL, in optc1_read_otg_state()
1346 OTG_V_TOTAL, &s->v_total); in optc1_read_otg_state()
1623 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn10_timing_generator_init()
Ddcn10_optc.h47 SRI(OTG_V_TOTAL, OTG, inst),\
119 uint32_t OTG_V_TOTAL; member
231 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
370 type OTG_V_TOTAL;\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn301/
Ddcn301_optc.c179 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn301_timing_generator_init()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn201/
Ddcn201_optc.c190 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn201_timing_generator_init()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn314/
Ddcn314_optc.h47 SRI(OTG_V_TOTAL, OTG, inst),\
125 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
Ddcn314_optc.c265 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn314_timing_generator_init()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn31/
Ddcn31_optc.h46 SRI(OTG_V_TOTAL, OTG, inst),\
126 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
Ddcn31_optc.c316 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn31_timing_generator_init()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn30/
Ddcn30_optc.h48 SRI(OTG_V_TOTAL, OTG, inst),\
138 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
Ddcn30_optc.c385 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn30_timing_generator_init()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn32/
Ddcn32_optc.c384 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn32_timing_generator_init()
Ddcn32_optc.h53 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn35/
Ddcn35_optc.c449 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn35_timing_generator_init()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn401/
Ddcn401_optc.h32 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
Ddcn401_optc.c504 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn401_timing_generator_init()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn20/
Ddcn20_optc.c572 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn20_timing_generator_init()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/
Ddcn35_resource.h232 SRI_ARR(OTG_V_TOTAL, OTG, inst),\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/
Ddcn401_resource.h490 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource.h1008 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \