| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| D | smu9_driver_if.h | 44 #define NUM_LINK_LEVELS 2 macro
53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
237 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
238 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
239 …uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
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| D | smu11_driver_if.h | 48 #define NUM_LINK_LEVELS 2 macro
63 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
453 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
454 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
455 uint16_t LclkFreq[NUM_LINK_LEVELS];
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/ |
| D | smu9_driver_if.h | 46 #define NUM_LINK_LEVELS 2 macro
59 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
341 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];
342 uint8_t PcieLaneCount[NUM_LINK_LEVELS];
343 uint16_t LclkFreq[NUM_LINK_LEVELS];
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu11_driver_if_sienna_cichlid.h | 47 #define NUM_LINK_LEVELS 2 macro
66 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
756 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
757 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
758 uint16_t LclkFreq[NUM_LINK_LEVELS];
1116 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
1117 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1118 uint16_t LclkFreq[NUM_LINK_LEVELS];
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| D | smu11_driver_if_navi10.h | 47 #define NUM_LINK_LEVELS 2 macro
62 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)
626 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
627 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
628 uint16_t LclkFreq[NUM_LINK_LEVELS];
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| D | smu13_driver_if_v13_0_0.h | 43 #define NUM_LINK_LEVELS 3 macro
1136 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
1137 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1138 uint16_t LclkFreq[NUM_LINK_LEVELS];
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| D | smu13_driver_if_v13_0_7.h | 44 #define NUM_LINK_LEVELS 3 macro
1138 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:P…
1139 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1140 uint16_t LclkFreq[NUM_LINK_LEVELS];
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| D | smu14_driver_if_v14_0.h | 41 #define NUM_LINK_LEVELS 3 macro
1231 …uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:…
1232 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1233 uint16_t LclkFreq[NUM_LINK_LEVELS];
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega20_processpptables.c | 398 for (i = 0; i < NUM_LINK_LEVELS; i++)
402 for (i = 0; i < NUM_LINK_LEVELS; i++)
406 for (i = 0; i < NUM_LINK_LEVELS; i++)
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| D | vega10_hwmgr.c | 1272 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_setup_default_pcie_table()
1294 pcie_table->count = NUM_LINK_LEVELS; in vega10_setup_default_pcie_table()
1548 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_override_pcie_parameters()
1557 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_override_pcie_parameters()
1588 while (i < NUM_LINK_LEVELS) { in vega10_populate_smc_link_levels()
4763 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_emit_clock_levels()
4907 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_print_clock_levels()
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| D | vega20_hwmgr.c | 876 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega20_override_pcie_parameters()
900 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega20_override_pcie_parameters()
2710 if (soft_min_level >= NUM_LINK_LEVELS || in vega20_force_clock_level()
2711 soft_max_level >= NUM_LINK_LEVELS) in vega20_force_clock_level()
3472 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega20_print_clock_levels()
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| D | vega12_hwmgr.c | 530 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega12_override_pcie_parameters()
554 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega12_override_pcie_parameters()
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | sienna_cichlid_ppt.c | 1353 for (i = 0; i < NUM_LINK_LEVELS; i++) in sienna_cichlid_print_clk_levels()
2138 for (i = 0; i < NUM_LINK_LEVELS; i++) { in sienna_cichlid_update_pcie_parameters()
2850 for (i = 0; i < NUM_LINK_LEVELS; i++) in beige_goby_dump_pptable()
2854 for (i = 0; i < NUM_LINK_LEVELS; i++) in beige_goby_dump_pptable()
2858 for (i = 0; i < NUM_LINK_LEVELS; i++) in beige_goby_dump_pptable()
3489 for (i = 0; i < NUM_LINK_LEVELS; i++) in sienna_cichlid_dump_pptable()
3493 for (i = 0; i < NUM_LINK_LEVELS; i++) in sienna_cichlid_dump_pptable()
3497 for (i = 0; i < NUM_LINK_LEVELS; i++) in sienna_cichlid_dump_pptable()
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| D | navi10_ppt.c | 1342 for (i = 0; i < NUM_LINK_LEVELS; i++) { in navi10_emit_clk_levels()
1544 for (i = 0; i < NUM_LINK_LEVELS; i++) in navi10_print_clk_levels()
2418 for (i = 0; i < NUM_LINK_LEVELS; i++) { in navi10_update_pcie_parameters()
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | smu_v13_0_7_ppt.c | 691 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { in smu_v13_0_7_set_default_dpm_table()
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| D | smu_v13_0_0_ppt.c | 693 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { in smu_v13_0_0_set_default_dpm_table()
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| D | smu_v14_0_2_ppt.c | 624 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { in smu_v14_0_2_set_default_dpm_table()
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