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Searched refs:MICROSECOND_TIME_BASE_DIV (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_i2c_hw.h96 SR(MICROSECOND_TIME_BASE_DIV)
141 I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\
142 I2C_SF(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, mask_sh),\
186 uint8_t MICROSECOND_TIME_BASE_DIV; member
231 uint32_t MICROSECOND_TIME_BASE_DIV; member
268 uint32_t MICROSECOND_TIME_BASE_DIV; member
Ddce_i2c_hw.c271 REG_GET_2(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, &ref_base_div, in set_speed()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dce/
Ddce_hwseq.h264 SR(MICROSECOND_TIME_BASE_DIV), \
328 SR(MICROSECOND_TIME_BASE_DIV), \
375 SR(MICROSECOND_TIME_BASE_DIV), \
399 SR(MICROSECOND_TIME_BASE_DIV), \
436 SR(MICROSECOND_TIME_BASE_DIV), \
488 SR(MICROSECOND_TIME_BASE_DIV), \
548 SR(MICROSECOND_TIME_BASE_DIV), \
638 uint32_t MICROSECOND_TIME_BASE_DIV; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
Ddcn21_hwseq.c93 value = REG_READ(MICROSECOND_TIME_BASE_DIV); in dcn21_s0i3_golden_init_wa()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/
Ddcn35_resource.h181 SR(MICROSECOND_TIME_BASE_DIV), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn316/
Ddcn316_resource.c691 SR(MICROSECOND_TIME_BASE_DIV), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn314/
Ddcn314_resource.c704 SR(MICROSECOND_TIME_BASE_DIV), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn321/
Ddcn321_resource.c544 SR(MICROSECOND_TIME_BASE_DIV), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn315/
Ddcn315_resource.c696 SR(MICROSECOND_TIME_BASE_DIV), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn31/
Ddcn31_resource.c697 SR(MICROSECOND_TIME_BASE_DIV), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/
Ddcn401_resource.c527 SR(MICROSECOND_TIME_BASE_DIV), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource.h1267 SR_ARR_I2C(DC_I2C_DATA, id), SR_ARR_I2C(MICROSECOND_TIME_BASE_DIV, id)
Ddcn32_resource.c547 SR(MICROSECOND_TIME_BASE_DIV), \
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
Ddcn20_hwseq.c357 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); in dcn20_dccg_init()