| /linux-6.12.1/Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
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| /linux-6.12.1/drivers/media/dvb-frontends/ |
| D | dvb-pll.c | 74 .min = 177 * MHz,
75 .max = 858 * MHz,
96 .min = 177 * MHz,
97 .max = 896 * MHz,
120 .min = 185 * MHz,
121 .max = 900 * MHz,
138 .min = 174 * MHz,
139 .max = 862 * MHz,
154 .min = 174 * MHz,
155 .max = 862 * MHz,
[all …]
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| D | dvb_dummy_fe.c | 216 .frequency_min_hz = 51 * MHz,
217 .frequency_max_hz = 858 * MHz,
250 .frequency_min_hz = 950 * MHz,
251 .frequency_max_hz = 2150 * MHz,
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| /linux-6.12.1/Documentation/userspace-api/media/dvb/ |
| D | fe-bandwidth-t.rst | 34 - 1.712 MHz
42 - 5 MHz
50 - 6 MHz
58 - 7 MHz
66 - 8 MHz
74 - 10 MHz
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| /linux-6.12.1/Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
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| /linux-6.12.1/arch/arm64/boot/dts/exynos/ |
| D | exynos5433-tmu.dtsi | 56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
242 /* Set maximum frequency as 1000MHz */
[all …]
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| /linux-6.12.1/drivers/staging/sm750fb/ |
| D | ddk750_chip.c | 9 #define MHz(x) ((x) * 1000000) macro
40 return MHz(130); in get_mxclk_freq()
101 if (frequency > MHz(336)) in set_memory_clock()
102 frequency = MHz(336); in set_memory_clock()
153 if (frequency > MHz(190)) in set_master_clock()
154 frequency = MHz(190); in set_master_clock()
240 set_chip_clock(MHz((unsigned int)p_init_param->chip_clock)); in ddk750_init_hw()
243 set_memory_clock(MHz(p_init_param->mem_clock)); in ddk750_init_hw()
246 set_master_clock(MHz(p_init_param->master_clock)); in ddk750_init_hw()
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| /linux-6.12.1/drivers/media/firewire/ |
| D | firedtv-fe.c | 173 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
174 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
193 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
194 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
213 fi->frequency_min_hz = 47 * MHz; in fdtv_frontend_init()
214 fi->frequency_max_hz = 866 * MHz; in fdtv_frontend_init()
231 fi->frequency_min_hz = 49 * MHz; in fdtv_frontend_init()
232 fi->frequency_max_hz = 861 * MHz; in fdtv_frontend_init()
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| /linux-6.12.1/arch/arm/boot/dts/arm/ |
| D | integratorcp.dts | 49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
297 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
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| /linux-6.12.1/Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
425 Specify clos max in MHz with [--max|-m]
434 clos min is not specified, default: 0 MHz
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/rockchip/ |
| D | rk3288-veyron-mickey.dts | 86 * and don't let the GPU go faster than 400 MHz.
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
139 /* At very hot, don't let GPU go over 300 MHz */
180 /* After 1st level throttle the GPU down to as low as 400 MHz */
200 /* When hot, GPU goes down to 300 MHz */
206 /* When really hot, don't let GPU go _above_ 300 MHz */
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| /linux-6.12.1/drivers/media/tuners/ |
| D | qt1010_priv.h | 70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| /linux-6.12.1/Documentation/userspace-api/media/drivers/ |
| D | max2175.rst | 53 samples/sec with a 10.24 MHz sck.
56 samples/sec with a 32.768 MHz sck.
61 samples/sec with a 14.88375 MHz sck.
64 samples/sec with a 7.441875 MHz sck.
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| /linux-6.12.1/Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 29 /* 12MHz, 24MHz and 48MHz allowed */
|
| /linux-6.12.1/arch/powerpc/boot/dts/ |
| D | media5200.dts | 29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
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| D | gamecube.dts | 34 clock-frequency = <486000000>; /* 486MHz */
35 bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */
36 timebase-frequency = <40500000>; /* 162MHz / 4 */
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| /linux-6.12.1/arch/mips/jazz/ |
| D | Kconfig | 7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
18 This is a machine with a R4000 100 MHz CPU. To compile a Linux
28 This is a machine with a R4000 100 MHz CPU. To compile a Linux
|
| /linux-6.12.1/arch/arm/mach-pxa/ |
| D | sleep.S | 67 @ with core operating above 91 MHz
104 @ about suspending with PXBus operating above 133MHz
124 orrne r7, r7, #1 @@ 99.53MHz
151 @ need 6 13-MHz cycles before changing PWRMODE
152 @ just set frequency to 91-MHz... 6*91/13 = 42
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| /linux-6.12.1/arch/arm/boot/dts/samsung/ |
| D | exynos5422-odroid-core.dtsi | 45 /* derived from 532MHz MPLL */
71 /* derived from 666MHz CPLL */
89 /* derived from 666MHz CPLL */
101 /* derived from 600MHz DPLL */
116 /* derived from 666MHz CPLL */
137 /* derived from 532MHz MPLL */
155 /* derived from 666MHz CPLL */
164 /* derived from 666MHz CPLL */
185 /* derived from 532MHz MPLL */
203 /* derived from 600MHz DPLL */
[all …]
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-platform-dptf | 104 (RW) The PCH FIVR (Fully Integrated Voltage Regulator) switching frequency in MHz,
105 when FIVR clock is 19.2MHz or 24MHz.
112 (RW) The PCH FIVR (Fully Integrated Voltage Regulator) switching frequency in MHz,
113 when FIVR clock is 38.4MHz.
120 (RO) Get the FIVR switching control frequency in MHz.
|
| /linux-6.12.1/tools/testing/selftests/intel_pstate/ |
| D | run.sh | 65 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
103 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
107 [ $EVALUATE_ONLY -eq 0 ] && cpupower frequency-set -g powersave --max=${max_freq}MHz >& /dev/null
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| /linux-6.12.1/Documentation/scsi/ |
| D | aic7xxx.rst | 26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
[all …]
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| /linux-6.12.1/Documentation/arch/arm/sunxi/ |
| D | clocks.rst | 8 Q: Why is the main 24MHz oscillator gateable? Wouldn't that break the
11 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
18 24MHz 32kHz
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| /linux-6.12.1/drivers/clk/ |
| D | kunit_clk_parent_data_test.dtso | 8 fixed_50: kunit-clock-50MHz {
15 fixed_parent: kunit-clock-1MHz {
|