Searched refs:MC_SEQ_WR_CTL_D0 (Results 1 – 12 of 12) sorted by relevance
111 #define MC_SEQ_WR_CTL_D0 0x28bc macro
1848 case MC_SEQ_WR_CTL_D0 >> 2: in btc_check_s0_mc_reg_index()2006 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in btc_initialize_mc_reg_table()
787 #define MC_SEQ_WR_CTL_D0 0x28bc macro
548 #define MC_SEQ_WR_CTL_D0 0x28bc macro
661 #define MC_SEQ_WR_CTL_D0 0x28bc macro
293 #define MC_SEQ_WR_CTL_D0 0x28bc macro
4404 case MC_SEQ_WR_CTL_D0 >> 2: in ci_check_s0_mc_reg_index()4516 case MC_SEQ_WR_CTL_D0: in ci_register_patching_mc_seq()4605 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in ci_initialize_mc_reg_table()
2794 case MC_SEQ_WR_CTL_D0 >> 2: in ni_check_s0_mc_reg_index()2893 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in ni_initialize_mc_reg_table()
999 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2; in cypress_set_mc_reg_address_table()
5385 case MC_SEQ_WR_CTL_D0 >> 2: in si_check_s0_mc_reg_index()5488 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in si_initialize_mc_reg_table()
549 #define MC_SEQ_WR_CTL_D0 0xA2F macro
5918 case MC_SEQ_WR_CTL_D0: in si_check_s0_mc_reg_index()6021 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in si_initialize_mc_reg_table()